Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems

2016 ◽  
Author(s):  
Hari Cherupalli ◽  
Rakesh Kumar ◽  
John Sartori
Keyword(s):  
Energy Efficiency ◽  
Embedded Systems ◽  
Low Power ◽  
Ultra Low Power

scholarly journals Level Converters for Ultra Low Power IoT Applications

2018 ◽  
Vol 7 (2.16) ◽  
pp. 19
Author(s):  
T Yugendra Chary ◽  
S Anitha ◽  
M Alamillo ◽  
Ameet Chavan
Keyword(s):  
Energy Efficiency ◽  
Low Power ◽  
Slight Reduction ◽  
Dramatic Improvement ◽  
Modest Improvement ◽  
Ultra Low Power ◽  
Iot Applications ◽  
Communication Devices ◽  
And Performance ◽  
Level Converter

For efficient ultra-low power IoT applications, working with various communication devices and sensors which operating voltages  from subthreshold to superthreshold levels which requires wide variety of robust level converters for signal interfacing with low power dissipation. This paper proposes two topologies of level converter circuits that offer dramatic improvement in power and performance when compared to the existing level converters that shift signals from sub to super threshold levels for IoT applications. At 250 mV, the first proposed circuit - a modification of a tradition al current mirror level converter - offers the best energy efficiency with approximately seven times less energy consumption per operation than the existing design, but suffers from a slight reduction in performance.  However, a second proposed circuit - based on a two-stage level converter - at the same voltage enhances performance by several orders of magnitude while still maintaining a modest improvement in energy efficiency.  The Energy Delay Products (EDP) of the two proposed designs are equivalent and are approximately four times better than the best existing design.  Consequently, the two circuit options either optimizes power or performance with improved overall EDP.  

Balancing resiliency and energy efficiency of functional units in ultra-low power systems

2018 ◽  
Author(s):  
Mohammad Saber Golanbari ◽  
Anteneh Gebregiorgis ◽  
Elyas Moradi ◽  
Saman Kiamehr ◽  
Mehdi B. Tahoori
Keyword(s):  
Energy Efficiency ◽  
Power Systems ◽  
Low Power ◽  
Ultra Low Power ◽  
Functional Units

scholarly journals Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 349-363
Author(s):  
V. A. Bartlett ◽  
E. Grass
Keyword(s):  
Energy Efficiency ◽  
Energy Consumption ◽  
Low Power ◽  
Energy Efficient ◽  
Dynamic Logic ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Data Dependencies ◽  
Simulation Results ◽  
Asynchronous Environments

Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's complement operands are introduced. Area overheads of the proposed designs are estimated and transistor level simulation results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.Normalized comparisons with other designs show our approach to use less energy than other published multipliers.

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