scholarly journals Side-channel vulnerability factor: A metric for measuring information leakage

2012 ◽  
Author(s):  
John Demme ◽  
Robert Martin ◽  
Adam Waksman ◽  
Simha Sethumadhavan
Keyword(s):  
Information Leakage ◽  
Side Channel ◽  
Vulnerability Factor

Power Side-Channel Analysis of RNS GLV ECC Using Machine and Deep Learning Algorithms

2021 ◽  
Vol 21 (3) ◽  
pp. 1-20
Author(s):  
Mohamad Ali Mehrabi ◽  
Naila Mukhtar ◽  
Alireza Jolfaei
Keyword(s):  
Deep Learning ◽  
Elliptic Curve ◽  
Smart Cities ◽  
Information Leakage ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Public Key Cryptosystems ◽  
Elliptic Curve Cryptosystems ◽  
Hardware Implementations ◽  
Substantial Progress

Many Internet of Things applications in smart cities use elliptic-curve cryptosystems due to their efficiency compared to other well-known public-key cryptosystems such as RSA. One of the important components of an elliptic-curve-based cryptosystem is the elliptic-curve point multiplication which has been shown to be vulnerable to various types of side-channel attacks. Recently, substantial progress has been made in applying deep learning to side-channel attacks. Conceptually, the idea is to monitor a core while it is running encryption for information leakage of a certain kind, for example, power consumption. The knowledge of the underlying encryption algorithm can be used to train a model to recognise the key used for encryption. The model is then applied to traces gathered from the crypto core in order to recover the encryption key. In this article, we propose an RNS GLV elliptic curve cryptography core which is immune to machine learning and deep learning based side-channel attacks. The experimental analysis confirms the proposed crypto core does not leak any information about the private key and therefore it is suitable for hardware implementations.

A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

2018 ◽  
Vol 23 (5) ◽  
pp. 1-30 ◽  
Author(s):  
Davide Zoni ◽  
Alessandro Barenghi ◽  
Gerardo Pelosi ◽  
William Fornaciari
Keyword(s):  
Information Leakage ◽  
Side Channel ◽  
Channel Information

Design Time Engineering of Side Channel Resistant Cipher Implementations

2013 ◽  
pp. 133-157 ◽  
Author(s):  
Alessandro Barenghi ◽  
Luca Breveglieri ◽  
Fabrizio De Santis ◽  
Filippo Melzani ◽  
Andrea Palomba ◽  
...  
Keyword(s):  
Power Consumption ◽  
Information Leakage ◽  
Smart Phones ◽  
Mobile Systems ◽  
Side Channel ◽  
Security Level ◽  
Embedded Devices ◽  
Design Time ◽  
Secret Keys ◽  
Channel Information

Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in modern Information Systems (IS). Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show how these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound conservative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched.

scholarly journals A novel side-channel analysis for physical-domain security in cyber-physical systems

2019 ◽  
Vol 15 (8) ◽  
pp. 155014771986786 ◽  
Author(s):  
Min Wang ◽  
Kama Huang ◽  
Yi Wang ◽  
Zhen Wu ◽  
Zhibo Du
Keyword(s):  
Information Leakage ◽  
Cyber Physical Systems ◽  
Cyber Attacks ◽  
Side Channel ◽  
Learning Technology ◽  
Physical Domain ◽  
Secret Key ◽  
Side Channel Analysis ◽  
Physical Systems ◽  
Channel Analysis

Security of cyber-physical systems against cyber attacks is an important yet challenging problem. Cyber-physical systems are prone to information leakage from the physical domain. The analog emissions, such as magnetic and power, can turn into side channel revealing valuable data, even the crypto key of the system. Template attack is a popular type of side-channel analysis using machine learning technology. Malicious attackers can use template attack to profile the analog emission, then recover the secret key of the system. But conventional template attack requires that the adversary has access to an identical experiment device that he can program to his choice. This study proposes a novel side-channel analysis for physical-domain security in cyber-physical systems. Our contributions are the following three points: (1) Major peak region method for finding points of interests correctly is proposed. (2) A method for establishing templates on the basis of those points of interest still without requiring knowledge of the key is proposed. Several techniques are proposed to improve the quality of the templates as well. (3) A method for choosing attacking traces is proposed to significantly improve the attacking efficiency. Our experiments on three devices show that the proposed method is significantly more effective than conventional template attack. By doing so, we will highlight the importance of performing similar analysis during design time to secure the cyber-physical system.

scholarly journals Attacking and Defending Masked Polynomial Comparison for Lattice-Based Cryptography

2021 ◽  
pp. 334-359
Author(s):  
Shivam Bhasin ◽  
Jan-Pieter D’Anvers ◽  
Daniel Heinz ◽  
Thomas Pöppelmann ◽  
Michiel Van Beirendonck
Keyword(s):  
Information Leakage ◽  
Side Channel ◽  
Side Channel Attacks ◽  
First Order ◽  
Comparison Operation ◽  
Security Properties ◽  
Channel Information ◽  
Comparison Algorithms ◽  
Lattice Based Cryptography ◽  
Do So

In this work, we are concerned with the hardening of post-quantum key encapsulation mechanisms (KEM) against side-channel attacks, with a focus on the comparison operation required for the Fujisaki-Okamoto (FO) transform. We identify critical vulnerabilities in two proposals for masked comparison and successfully attack the masked comparison algorithms from TCHES 2018 and TCHES 2020. To do so, we use first-order side-channel attacks and show that the advertised security properties do not hold. Additionally, we break the higher-order secured masked comparison from TCHES 2020 using a collision attack, which does not require side-channel information. To enable implementers to spot such flaws in the implementation or underlying algorithms, we propose a framework that is designed to test the re-encryption step of the FO transform for information leakage. Our framework relies on a specifically parametrized t-test and would have identified the previously mentioned flaws in the masked comparison. Our framework can be used to test both the comparison itself and the full decapsulation implementation.

scholarly journals Cache Misses and the Recovery of the Full AES 256 Key

2019 ◽  
Author(s):  
Samira Briongos ◽  
Pedro Malagón ◽  
Juan-Mariano de Goyeneche ◽  
Jose M. Moya
Keyword(s):  
Cloud Computing ◽  
Information Leakage ◽  
Side Channel ◽  
Sensitive Information ◽  
Sources Of Information ◽  
Shared Cache ◽  
Novel Approach ◽  
Memory Accesses ◽  
Cache Attacks

In recent years, CPU caches have revealed themselves as one of the most powerful sources of information leakage. This information leakage affects any implementation whose memory accesses, to data or instructions, depend on sensitive information such as private keys. In most cases, side-channel cache attacks do not require any specific permission and just need access to a shared cache. This fact, combined with the spread of cloud computing, where the infrastructure is shared between different customers, have made these attacks quite popular. In this paper, we present a novel approach to exploit the information obtained from the CPU cache. First, we introduce a non-access attack that provides a 97\% reduction in the number of encryptions required to obtain a 128-bit AES key. Next, this attack is adapted and extended in what we call the encryption-by-decryption cache attack or EBD, to obtain a 256-bit AES key. When EBD is applied to AES-256, we are able to obtain the 256 bits of the key with less than 10000 encryptions. These results make EBD, to the best of our knowledge, the first practical attack on AES-256 and also demonstrate that AES-256 is only about 3 times more complex to attack than AES-128 via cache attacks. In both cases the target is the AES T-table-based implementation, and we also demonstrate that our approach works in a cross-VM scenario.

scholarly journals Towards Efficient and Automated Side Channel Evaluations at Design Time

10.29007/mbf3 ◽  
2018 ◽  
Author(s):  
Danilo Šijačić ◽  
Josep Balasch ◽  
Bohan Yang ◽  
Santosh Ghosh ◽  
Ingrid Verbauwhede
Keyword(s):  
Experimental Validation ◽  
State Of The Art ◽  
Information Leakage ◽  
Design Flow ◽  
Side Channel ◽  
Cell Design ◽  
Standard Cell ◽  
Side Channel Analysis ◽  
Design Time ◽  
Channel Analysis

Models and tools developed by the semiconductor community have matured over decades of use. As a result, hardware simulations can yield highly accurate and easily automated pre-silicon estimates for e.g. timing and area figures. In this work we design, implement, and evaluate CASCADE, a framework that combines a largely automated full-stack standard-cell design flow with the state of the art techniques for side channel analysis. We show how it can be used to efficiently evaluate side channel leakage prior to chip manufacturing. Moreover, it is independent of the underlying countermeasure and it can be applied starting from the earliest stages of the design flow. Additionally, we provide experimental validation through assessment of the side channel security of representative cryptographic circuits. We discuss aspects related to the performance, scalability, and utility to the designers. In particular, we show that CASCADE can evaluate information leakage with 1 million simulated traces in less than 4 hours using a single desktop workstation, for a design larger than 100kGE.

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