Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors

2002 ◽  
Author(s):  
Chi-Keung Luk
Keyword(s):  
Memory Latency ◽  
Simultaneous Multithreading

A Simple Model to Quantify the Impact of Memory Latency and Bandwidth on Performance

2015 ◽  
Vol 43 (1) ◽  
pp. 471-472
Author(s):  
Russell Clapp ◽  
Martin Dimitrov ◽  
Karthik Kumar ◽  
Vish Viswanathan ◽  
Thomas Willhalm
Keyword(s):  
Simple Model ◽  
Memory Latency ◽  
The Impact

SYSTEMC IMPLEMENTATION AND PERFORMANCE EVALUATION OF A DECOUPLED GENERAL-PURPOSE MATRIX PROCESSOR

2010 ◽  
Vol 20 (02) ◽  
pp. 103-121 ◽  
Author(s):  
MOSTAFA I. SOLIMAN ◽  
ABDULMAJID F. Al-JUNAID
Keyword(s):  
Performance Evaluation ◽  
Matrix Multiplication ◽  
General Purpose ◽  
System Level ◽  
Memory Latency ◽  
Single Chip ◽  
Wide Range ◽  
Matrix Unit ◽  
And Performance ◽  
Vector Matrix

Technological advances in IC manufacturing provide us with the capability to integrate more and more functionality into a single chip. Today's modern processors have nearly one billion transistors on a single chip. With the increasing complexity of today's system, the designs have to be modeled at a high-level of abstraction before partitioning into hardware and software components for final implementation. This paper explains in detail the implementation and performance evaluation of a matrix processor called Mat-Core with SystemC (system level modeling language). Mat-Core is a research processor aiming at exploiting the increasingly number of transistors per IC to improve the performance of a wide range of applications. It extends a general-purpose scalar processor with a matrix unit. To hide memory latency, the extended matrix unit is decoupled into two components: address generation and data computation, which communicate through data queues. Like vector architectures, the data computation unit is organized in parallel lanes. However, on parallel lanes, Mat-Core can execute matrix-scalar, matrix-vector, and matrix-matrix instructions in addition to vector-scalar and vector-vector instructions. For controlling the execution of vector/matrix instructions on the matrix core, this paper extends the well known scoreboard technique. Furthermore, the performance of Mat-Core is evaluated on vector and matrix kernels. Our results show that the performance of four lanes Mat-Core with matrix registers of size 4 × 4 or 16 elements each, queues size of 10, start up time of 6 clock cycles, and memory latency of 10 clock cycles is about 0.94, 1.3, 2.3, 1.6, 2.3, and 5.5 FLOPs per clock cycle; achieved on scalar-vector multiplication, SAXPY, Givens, rank-1 update, vector-matrix multiplication, and matrix-matrix multiplication, respectively.

Asynchronous PRAMS with Memory Latency

1994 ◽  
Vol 23 (1) ◽  
pp. 10-26 ◽  
Author(s):  
C. Martel ◽  
A. Raghunathan
Keyword(s):  
Memory Latency ◽  
With Memory

SMT-SA: Simultaneous Multithreading in Systolic Arrays

2019 ◽  
Vol 18 (2) ◽  
pp. 99-102 ◽  
Author(s):  
Gil Shomron ◽  
Tal Horowitz ◽  
Uri Weiser
Keyword(s):  
Systolic Arrays ◽  
Simultaneous Multithreading
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