Study on sensitive character of unexpected high impedance circuit in VLSI failure analysis

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

Download Full-text

Case Study on Abnormal Electron-Optical Frequency Mapping Phenomena in Failure Analysis

10.31399/asm.cp.istfa2018p0156 ◽

2018 ◽

Author(s):

Ang Li ◽

Ryan Xiao ◽

Max Guo ◽

Jinglong Li ◽

Binghai Liu

Keyword(s):

Failure Analysis ◽

Short Circuit ◽

Mapping Technique ◽

Optical Frequency ◽

Substrate Noise ◽

Noise Current ◽

High Impedance ◽

Laser Reflectance ◽

Circuit Defects

Abstract In recent years, laser reflectance modulation measurements are widely used in failure analysis. Among them, EOFM (Electron-Optical Frequency Mapping) technique is easy to operate and very practical. In this article, some images with abnormal EOFM phenomena and their corresponding defects are showing up, the causes of those abnormal EOFM phenomena are also pointed out. They prove that EOFM function is very effective for discovering open or high-impedance defects on metal trace and pinpointing short-circuit defects. In addition to the two aspects above, there are also some abnormal EOFM phenomena we couldn’t explain perfectly. We studied one of them and proposed two possible causes of the anomaly. After simulation experiment and calculation, it could be basically determined that the abnormal EOFM phenomenon was caused by the substrate noise current.

Download Full-text

Methodologies for Isolating Faults in Multi Chip Fiber Optic Transceivers That Use GHz Mixed Signal ICs

ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2002p0251 ◽

2002 ◽

Author(s):

Kuhn Seo ◽

Brent Wahl ◽

Myrna Mayonte ◽

Young Gon Kim

Keyword(s):

Integrated Circuits ◽

Failure Analysis ◽

Fiber Optic ◽

Digital Signals ◽

Mixed Signal ◽

Loading Effect ◽

High Impedance ◽

Single Probe ◽

Data Signal ◽

Rf Signal

Abstract This paper outlines a methodology which accurately identifies fault locations in Mixed Signal Integrated Circuits (ICs). The architecture of Mixed Signal ICs demands more attention during failure analysis because of the complexity of measuring both the analog and digital signals in a compact circuit. In this paper, the GHz range of data signal or radio frequency (RF) signal from an internal IC circuit will be extracted by a high-impedance active single probe in order to find the internal IC circuit failure locations. The advantages of using a single probe is that it can maneuver to extract data almost anywhere in the circuit, providing ranges of bandwidth in GHz with no loading effect on the circuits during measurement. The process of preparing a sample and extracting a signal will be described.

Download Full-text

Failure Analysis With the Scanning Electron Microscope

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100095662 ◽

1972 ◽

Vol 30 ◽

pp. 482-483

Author(s):

John R. Devaney

Keyword(s):

Electron Microscope ◽

Scanning Electron Microscope ◽

Integrated Circuits ◽

Failure Analysis ◽

High Reliability ◽

Military Applications ◽

Small Structure ◽

Useful Life ◽

Insight Into ◽

Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

Download Full-text

Using the scanning electron microscope for failure analysis of high density magnetic media

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100126755 ◽

1987 ◽

Vol 45 ◽

pp. 392-393

Author(s):

Evelyn R. Ackerman ◽

Gary D. Burnett

Keyword(s):

Electron Microscope ◽

Scanning Electron Microscope ◽

Failure Analysis ◽

High Density ◽

Magnetic Media ◽

Specific Data ◽

Retrieval Systems ◽

Operating Environments ◽

The Media ◽

Scanning Electron

Advancements in state of the art high density Head/Disk retrieval systems has increased the demand for sophisticated failure analysis methods. From 1968 to 1974 the emphasis was on the number of tracks per inch. (TPI) ranging from 100 to 400 as summarized in Table 1. This emphasis shifted with the increase in densities to include the number of bits per inch (BPI). A bit is formed by magnetizing the Fe203 particles of the media in one direction and allowing magnetic heads to recognize specific data patterns. From 1977 to 1986 the tracks per inch increased from 470 to 1400 corresponding to an increase from 6300 to 10,800 bits per inch respectively. Due to the reduction in the bit and track sizes, build and operating environments of systems have become critical factors in media reliability.Using the Ferrofluid pattern developing technique, the scanning electron microscope can be a valuable diagnostic tool in the examination of failure sites on disks.

Download Full-text