The application of scanning capacitance microscopy in device failure analysis [doping profile determination]

2004 ◽  
Author(s):  
Y.M. Lau ◽  
V.S.W. Lim ◽  
L.B. Ang ◽  
A. Trigg
Keyword(s):  
Failure Analysis ◽  
Doping Profile ◽  
Device Failure ◽  
Scanning Capacitance Microscopy

To Reveal Invisible Doping Defect by Nanoprobing Analysis, Scanning Capacitance Microscopy, and Simulation

2017 ◽  
Author(s):  
LiLung Lai ◽  
Li Yang ◽  
Chunhui Wang ◽  
Yong Wu
Keyword(s):  
Failure Analysis ◽  
Material Composition ◽  
Doping Profile ◽  
New Techniques ◽  
Great Opportunity ◽  
Scanning Capacitance Microscopy ◽  
Electrical Modeling ◽  
Scale Dimension ◽  
Physical Defects ◽  
Trace Concentrations

Abstract Modern techniques of semiconductor physical failure analysis are effective at revealing physical defects and device material composition, however, dopant profiles/ concentrations are not easily determined since these materials are in trace concentrations. Therefore, defects related to dopants are often referred to as invisible defects. New techniques have been incorporated into failure analysis to reveal the invisible defects resulting from electrical carriers (via SCM/SSRM) and physical doping profile (via STEM/EDS) in nm-scale dimension. Using nanoprobing analysis, simulation for electrical modeling, along with EDS and SCM for physical profiling, we have a great opportunity to uncover abnormal doping issues allowing completion of the failure analysis and the execution of corrective actions.

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

2018 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Tanya Schaeffer ◽  
Yuting Wei ◽  
Satish Kodali ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Scanning Capacitance Microscopy ◽  
Force Microscopy ◽  
Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

Analysis of Forward Surge Performance of SiC Schottky Diodes

2018 ◽  
Vol 924 ◽  
pp. 621-624 ◽  
Author(s):  
Rahul Radhakrishnan ◽  
Nathanael Cueva ◽  
Tony Witt ◽  
Richard L. Woodin
Keyword(s):  
Silicon Carbide ◽  
Failure Analysis ◽  
Ohmic Contact ◽  
Schottky Diodes ◽  
Forward Bias ◽  
Device Failure ◽  
Electrical Failure ◽  
The Impact ◽  
Surge Current

Silicon Carbide JBS diodes are capable, in forward bias, of carrying surge current of magnitude significantly higher than their rated current, for short periods. In this work, we examine the mechanisms of device failure due to excess surge current by analyzing variation of failure current with device current and voltage ratings, as well as duration of current surge. Physical failure analysis is carried out to correlate to electrical failure signature. We also quantify the impact, on surge current capability, of the resistance of the anode ohmic contact to the p-shielding region.

scholarly journals Device failure analysis by scanning electron microscopy

1969 ◽  
Vol 8 (1) ◽  
pp. 33-53 ◽  
Author(s):  
P.R. Thornton ◽  
I.G. Davies ◽  
D.A. Shaw ◽  
D.V. Sulway ◽  
R.C. Wayte
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Failure Analysis ◽  
Device Failure ◽  
Scanning Electron

Advanced CMOS Device Fault Isolation Using Frequency Mapping on Passive Structures

2013 ◽  
Author(s):  
S.H. Goh ◽  
B.L. Yeoh ◽  
G.F. You ◽  
W.H. Hung ◽  
Jeffrey Lam ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Device Failure ◽  
Functional Failure ◽  
Technology Node ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Scan Chains

Abstract Backside frequency mapping on modulating active in transistors is well established for defect localization on broken scan chains. Recent experiments have proven the existence of frequency signals from passive structures modulations. In this paper, we demonstrate the effectiveness of this technique on a 65 nm technology node device failure. A resistive leaky path leading to a functional failure which, otherwise cannot be isolated using dynamic emission microscopy, is localized in this work to guide follow on failure analysis.

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