Backside SC-OBIC using a pulsed NIR-laser and its application to fault location

2003 ◽  
Author(s):  
T. Beauchene ◽  
D. Lewis ◽  
F. Beaudoin ◽  
P. Perdu ◽  
P. Fouillat
Keyword(s):  
Fault Location ◽  
Nir Laser

Modeling of Air-gap Flux Inside of Generator for Fault Location

2012 ◽  
Vol 132 (10) ◽  
pp. 872-878
Author(s):  
Junya Matsuki ◽  
Hisao Taoka ◽  
Shoji Kawasaki ◽  
Yuki Nakajima ◽  
Masakazu Horime ◽  
...  
Keyword(s):  
Fault Location ◽  
Air Gap

Short-Circuit Fault Location Interval Recognition Criteria in Electrical System

2019 ◽  
Vol 11 ◽  
pp. 33-39
Author(s):  
Yury Ya. LYAMETS ◽  
◽  
Mikhail V. MARTYNOV ◽  
Alexander N. MASLOV ◽  
◽  
...  
Keyword(s):  
Fault Location ◽  
Short Circuit ◽  
Electrical System ◽  
Short Circuit Fault

FAULT LOCATION ESTIMATION SYSTEMS: A CRITICAL REVIEW

2017 ◽  
Vol 5 (3) ◽  
pp. 17
Author(s):  
SANAD A. AHMED ◽  
ATTIA MAHMOUD A. ◽  
HAMED NABIL M. ◽  
ABDELAZIZ ALMOATAZ Y. ◽  
◽  
...  
Keyword(s):  
Critical Review ◽  
Fault Location ◽  
Location Estimation

WLCSP Laminate Removal Using NIR Laser

2018 ◽  
Author(s):  
Chun Haur Khoo
Keyword(s):  
Near Infrared ◽  
Laser Energy ◽  
Photon Emission ◽  
Mechanical Damage ◽  
Consumer Products ◽  
Fault Isolation ◽  
Wafer Level ◽  
Isolation Technique ◽  
Laminate Layer ◽  
Nir Laser

Abstract Driven by the cost reduction and miniaturization, Wafer Level Chip Scale Packaging (WLCSP) has experienced significant growth mainly driven by mobile consumer products. Depending on the customers or manufacturing needs, the bare silicon backside of the WLCSP may be covered with a backside laminate layer. In the failure analysis lab, in order to perform the die level backside fault isolation technique using Photon Emission Microscope (PEM) or Laser Signal Injection Microscope (LSIM), the backside laminate layer needs to be removed. Most of the time, this is done using the mechanical polishing method. This paper outlines the backside laminate removal method of WLCSP using a near infrared (NIR) laser that produces laser energy in the 1,064 nm range. This method significantly reduces the sample preparation time and also reduces the risk of mechanical damage as there is no application of mechanical force. This is an effective method for WLCSP mounted on a PCB board.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Electronic Package Failure Analysis Using TDR

2000 ◽  
Author(s):  
Dima A. Smolyansky
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Measurement Accuracy ◽  
Time Domain Reflectometry ◽  
Acoustic Imaging ◽  
X Ray ◽  
Analysis Techniques ◽  
Bga Packages ◽  
Impedance Profile ◽  
Nature Of Time

Abstract The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.

IR Thermography for Temperature Measurements and Fault Location on AlGaN/GaN HEMTs and MMICs

2015 ◽  
Author(s):  
Lény Baczkowski ◽  
Franck Vouzelaud ◽  
Dominique Carisetti ◽  
Nicolas Sarazin ◽  
Jean-Claude Clément ◽  
...  
Keyword(s):  
Fault Location ◽  
Hot Spot ◽  
Life Time ◽  
High Electron Mobility Transistors ◽  
Junction Temperature ◽  
High Electron ◽  
Ir Thermography ◽  
Operating Life ◽  
Gan Hemt ◽  
Electron Mobility Transistors

Abstract This paper shows a specific approach based on infrared (IR) thermography to face the challenging aspects of thermal measurement, mapping, and failure analysis on AlGaN/GaN high electron-mobility transistors (HEMTs) and MMICs. In the first part of this paper, IR thermography is used for the temperature measurement. Results are compared with 3D thermal simulations (ANSYS) to validate the thermal model of an 8x125pm AIGaN/GaN HEMT on SiC substrate. Measurements at different baseplate temperature are also performed to highlight the non-linearity of the thermal properties of materials. Then, correlations between the junction temperature and the life time are also discussed. In the second part, IR thermography is used for hot spot detection. The interest of the system for defect localization on AIGaN/GaN HEMT technology is presented through two case studies: a high temperature operating life test and a temperature humidity bias test.

Towards High Accuracy Fault Diagnosis of Digital Circuits

2004 ◽  
Author(s):  
Camelia Hora ◽  
Stefan Eichenberger
Keyword(s):  
Fault Diagnosis ◽  
Fault Location ◽  
Digital Circuits ◽  
High Accuracy ◽  
Manufacturing Processes ◽  
Diagnosis Method ◽  
Technology Trend

Abstract Due to the development of smaller and denser manufacturing processes most of the hardware localization techniques cannot keep up satisfactorily with the technology trend. There is an increased need in precise and accurate software based diagnosis tools to help identify the fault location. This paper describes the software based fault diagnosis method used within Philips, focusing on the features developed to increase its accuracy.

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