The effect of nitrogen pre-annealing on the sidewall oxidation of WSi/sub x/ and on the related electrical properties of WSi/sub x//poly Si gate structure

1999 ◽  
Author(s):  
Dae-Hwan Kang ◽  
Hyeon-Soo Kim ◽  
Myung-Jun Chung ◽  
Kwang-Ho Ahn ◽  
Sang-Tae Chung ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Structure

High K / Metal Gate of Short-Channel SOI NMOSFET Research

2011 ◽  
Vol 383-390 ◽  
pp. 6902-6907
Author(s):  
Gang Lu ◽  
Bo Zhao
Keyword(s):  
Electrical Properties ◽  
Theoretical Analysis ◽  
Leakage Current ◽  
Device Performance ◽  
Gate Leakage Current ◽  
Metal Gate ◽  
Short Channel ◽  
Gate Structure ◽  
High K ◽  
Simulation Results

Short-channel under TaCN/La2O3gate structure SOI NMOSFET has been studied in this paper, contrast with the traditional gate structure gate leakage current and others electrical properties, using TaCN/La2O3gate structure，significantly improved short-channel device performance etc. Additionally, the gate structure in the L=40nm, 30nm and 20nm of C-V characteristic and output characteristic are also studied; all the simulation results coincide with the theoretical analysis.

Fabrication of Ferroelectric Fet with Metal/PZT/SiO2/Si Structure

1998 ◽  
Vol 526 ◽  
Author(s):  
Jun Yu ◽  
Wenli Zhou ◽  
Jifan Xie ◽  
Yuankai Zheng ◽  
Xiaoming Dong ◽  
...  
Keyword(s):  
Thin Film ◽  
Laser Ablation ◽  
Electrical Properties ◽  
Silicon Oxide ◽  
Si Substrate ◽  
Excimer Laser Ablation ◽  
Gate Structure ◽  
Pzt Thin Film ◽  
Ferroelectric Memory ◽  
Memory Characteristics

AbstractWe have fabricated a new ferroelectric memory FET, which consists of the Au/Pb(Zr0.52Ti0.48)O3/SiO2/Si gate structure. Ferroelectric PZT thin film with a thickness of 250~400 nm was prepared by using Excimer Laser Ablation Deposition. Silicon oxide successfully served as a buffer layer between ferroelectric and Si substrate to suppress the charge injection and prevent Pb interdiffusion. Electrical properties of the ferroelectric FET have been characterized through both the Capacitance vs. Voltage(C-V) and Current vs. Voltage(I-V) measurements, showing a typical memory characteristics of FET devices, i.e., the ON state and OFF state were nonvolatile for about thirty minutes and several hours, respectively.

scholarly journals Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure

2014 ◽  
Vol 9 (1) ◽  
pp. 669
Author(s):  
Ya-Chi Cheng ◽  
Hung-Bin Chen ◽  
Jun-Ji Su ◽  
Chi-Shen Shao ◽  
Cheng-Ping Wang ◽  
...  
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Thin Film Transistors ◽  
Gate Structure ◽  
Dual Gate

In situ TEM measurements of the electrical properties of interface dislocations

1992 ◽  
Vol 50 (2) ◽  
pp. 1338-1339
Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Electronic Device ◽  
In Situ Tem ◽  
Device Performance ◽  
Misfit Dislocations ◽  
Electrical Characteristics ◽  
Strained Layer ◽  
Transmission Electron ◽  
Interfacial Dislocations

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.

The morphologies and electrical properties of indium contacts on (100) cadmium telluride surfaces

1992 ◽  
Vol 50 (2) ◽  
pp. 1422-1423
Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs
Keyword(s):  
Electrical Properties ◽  
Cadmium Telluride ◽  
Methanol Solution ◽  
Electrical Characteristics ◽  
Metal Contacts ◽  
Deposition Technique ◽  
Interfacial Layers ◽  
Semiconductor Contacts ◽  
Grown Single Crystal ◽  
Diamond Abrasive

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.

Formation of high temperature phase in flash-evaporated SnSe films

1990 ◽  
Vol 48 (4) ◽  
pp. 698-699
Author(s):  
J.P.S. Hanjra
Keyword(s):  
Thin Films ◽  
Electrical Properties ◽  
Energy Gap ◽  
Dominant Role ◽  
Fine Powder ◽  
High Temperature Phase ◽  
Temperature Phase ◽  
Water Mixture ◽  
Flash Evaporation ◽  
Photovoltaic Applications

Tin mono selenide (SnSe) with an energy gap of about 1 eV is a potential material for photovoltaic applications. Various authors have studied the structure, electronic and photoelectronic properties of thin films of SnSe grown by various deposition techniques. However, for practical photovoltaic junctions the electrical properties of SnSe films need improvement. We have carried out investigations into the properties of flash evaporated SnSe films. In this paper we report our results on the structure, which plays a dominant role on the electrical properties of thin films by TEM, SEM, and electron diffraction (ED).Thin films of SnSe were deposited by flash evaporation of SnSe fine powder prepared from high purity Sn and Se, onto glass, mica and KCl substrates in a vacuum of 2Ø micro Torr. A 15% HF + 2Ø% HNO3 solution was used to detach SnSe film from the glass and mica substrates whereas the film deposited on KCl substrate was floated over an ethanol water mixture by dissolution of KCl. The floating films were picked up on the grids for their EM analysis.

The electrical properties of germanium semiconductors at low temperatures

Physica ◽  
1954 ◽  
Vol 3 (7-12) ◽  
pp. 834-844 ◽  
Author(s):  
H FRITZSCHE ◽  
K LARKHOROVITZ
Keyword(s):  
Electrical Properties ◽  
Low Temperatures
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