Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures

2017 ◽  
Author(s):  
Tripti Jain ◽  
Klaus Schneider ◽  
Frederik Walk
Keyword(s):  
Data Path ◽  
Order Execution

Reusable Data-Path Architecture for Encryption-then-Authentication on FPGA

2016 ◽  
Vol 11 (1) ◽  
pp. 56 ◽  
Author(s):  
Yasir Amer Abbas ◽  
Razali Jidin ◽  
Norziana Jamil ◽  
Muhammad Reza Z'aba
Keyword(s):  
Data Path

A methodology for performance driven data-path compilation

2002 ◽  
Author(s):  
S. Note ◽  
F. Catthoor ◽  
G. Goossens ◽  
H. De Man
Keyword(s):  
Data Path

scholarly journals OPMSS: Optimal Producer Mobility Support Solution for Named Data Networking

2021 ◽  
Vol 11 (9) ◽  
pp. 4064
Author(s):  
Muktar Hussaini ◽  
Muhammad Ali Naeem ◽  
Byung-Seo Kim
Keyword(s):  
Optimal Routing ◽  
Data Path ◽  
Named Data Networking ◽  
Packet Losses ◽  
Average Delay ◽  
Internet Architecture ◽  
Mobility Support ◽  
Signaling Overhead ◽  
Handoff Latency ◽  
Data Networking

Named data networking (NDN) is designed as a clean-slate Internet architecture to replace the current IP Internet architecture. The named data networking was proposed to offer vast advantages, especially with the advent of new content distributions in IoT, 5G and vehicular networking. However, the architecture is still facing challenges for managing content producer mobility. Despite the efforts of many researchers that curtailed the high handoff latency and signaling overhead, there are still some prominent challenges, such as non-optimal routing path, long delay for data delivery and unnecessary interest packet losses. This paper proposed a solution to minimize unnecessary interest packet losses, delay and provide data path optimization when the mobile producer relocates by using mobility update, broadcasting and best route strategies. The proposed solution is implemented, evaluated and benchmarked with an existing Kite solution. The performance analysis result revealed that our proposed Optimal Producer Mobility Support Solution (OPMSS) minimizes the number of unnecessary interest packets lost on average by 30%, and an average delay of 25% to 30%, with almost equal and acceptable signaling overhead costs. Furthermore, it provides a better data packet delivery route than the Kite solution.

A methodology for synthesis of data path circuits

2002 ◽  
Vol 19 (6) ◽  
pp. 90-100 ◽  
Author(s):  
A. Chowdhary ◽  
R.K. Gupta
Keyword(s):  
Data Path

A Novel HBE-MCM-Based Multiplier Architecture for 8-Point DCT Structure

2016 ◽  
Vol 26 (04) ◽  
pp. 1750054
Author(s):  
M. Kiruba ◽  
V. Sumathy
Keyword(s):  
Video Processing ◽  
Power Dissipation ◽  
Field Programmable Gate Array ◽  
Video Codec ◽  
Floating Point ◽  
Data Path ◽  
Image And Video Processing ◽  
Field Programmable ◽  
Minimum Number ◽  
Code Language

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.

Interrupt handling for out-of-order execution processors

1993 ◽  
Vol 42 (1) ◽  
pp. 122-127 ◽  
Author(s):  
H.C. Torng ◽  
M. Day
Keyword(s):  
Interrupt Handling ◽  
Order Execution
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