Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories

2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS) ◽

10.1109/ipdps.2016.84 ◽

2016 ◽

Cited By ~ 6

Author(s):

Juan Salamanca ◽

Jose Nelson Amaral ◽

Guido Araujo

Keyword(s):

Thread Level Speculation ◽

Transactional Memories

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Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories

Lecture Notes in Computer Science - Euro-Par 2017: Parallel Processing ◽

10.1007/978-3-319-64203-1_44 ◽

2017 ◽

pp. 607-621 ◽

Cited By ~ 1

Author(s):

Juan Salamanca ◽

José Nelson Amaral ◽

Guido Araujo

Keyword(s):

Performance Evaluation ◽

Thread Level Speculation ◽

Transactional Memories

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Reducing the Repairing Penalty on Misspeculation in Thread-Level Speculation

10.1145/3468081.3471120 ◽

2021 ◽

Author(s):

Hiroaki Hirata ◽

Atsushi Nunome

Keyword(s):

Thread Level Speculation

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Mechanical Verification of Transactional Memories with Non-transactional Memory Accesses

Computer Aided Verification - Lecture Notes in Computer Science ◽

10.1007/978-3-540-70545-1_13 ◽

2008 ◽

pp. 121-134 ◽

Cited By ~ 15

Author(s):

Ariel Cohen ◽

Amir Pnueli ◽

Lenore D. Zuck

Keyword(s):

Transactional Memory ◽

Mechanical Verification ◽

Memory Accesses ◽

Transactional Memories

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On Replication of Software Transactional Memories

Lecture Notes in Computer Science - Principles of Distributed Systems ◽

10.1007/978-3-540-92221-6_2 ◽

2008 ◽

pp. 2-4

Author(s):

Luis Rodrigues

Keyword(s):

Transactional Memories

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Support for Thread-Level Speculation into OpenMP

OpenMP in a Heterogeneous World - Lecture Notes in Computer Science ◽

10.1007/978-3-642-30961-8_25 ◽

2012 ◽

pp. 275-278 ◽

Cited By ~ 4

Author(s):

Sergio Aldea ◽

Diego R. Llanos ◽

Arturo González-Escribano

Keyword(s):

Thread Level Speculation

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Model checking transactional memories

ACM SIGPLAN Notices ◽

10.1145/1379022.1375626 ◽

2008 ◽

Vol 43 (6) ◽

pp. 372-382 ◽

Cited By ~ 5

Author(s):

Rachid Guerraoui ◽

Thomas A. Henzinger ◽

Barbara Jobstmann ◽

Vasu Singh

Keyword(s):

Model Checking ◽

Transactional Memories

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Software Thread Level Speculation for the Java Language and Virtual Machine Environment

Languages and Compilers for Parallel Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-540-69330-7_21 ◽

2006 ◽

pp. 304-318 ◽

Cited By ~ 13

Author(s):

Christopher J. F. Pickett ◽

Clark Verbrugge

Keyword(s):

Virtual Machine ◽

Java Language ◽

Thread Level Speculation

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Shelving a Code Block for Thread-Level Speculation

2019 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD) ◽

10.1109/snpd.2019.8935751 ◽

2019 ◽

Cited By ~ 1

Author(s):

Daiki Matsunaga ◽

Atsushi Nunome ◽

Hiroaki Hirata

Keyword(s):

Thread Level Speculation

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Energy-Efficient Thread-Level Speculation

IEEE Micro ◽

10.1109/mm.2006.11 ◽

2006 ◽

Vol 26 (1) ◽

pp. 80-91 ◽

Cited By ~ 10

Author(s):

J. Renau ◽

K. Strauss ◽

L. Ceze ◽

Wei Liu ◽

S.R. Sarangi ◽

...

Keyword(s):

Energy Efficient ◽

Thread Level Speculation

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Parallel genetic algorithm based on Thread-Level Speculation

2010 International Conference on Audio, Language and Image Processing ◽

10.1109/icalip.2010.5684374 ◽

2010 ◽

Author(s):

Zhao Wen-jiang ◽

Yang Hong-bin ◽

Wu Yue

Keyword(s):

Genetic Algorithm ◽

Parallel Genetic Algorithm ◽

Thread Level Speculation

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