Managing power, performance and reliability trade-offs

2008 IEEE International Symposium on Parallel and Distributed Processing ◽

10.1109/ipdps.2008.4536422 ◽

2008 ◽

Author(s):

Padma Raghavan ◽

Mahmut Kandemir ◽

Mary Jane Irwin ◽

Konrad Malkowski

Keyword(s):

Power Performance ◽

Trade Offs

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System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures

Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03 ◽

10.1145/951710.951722 ◽

2003 ◽

Cited By ~ 16

Author(s):

Juanjo Noguera ◽

Rosa M. Badia

Keyword(s):

Task Scheduling ◽

System Level ◽

Reconfigurable Architectures ◽

Power Performance ◽

Dynamically Reconfigurable ◽

Trade Offs

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Power Performance Trade- Offs in Design of SoCs

Computer Engineering Series - Low-Power Electronics Design ◽

10.1201/9781420039559.pt4 ◽

2004 ◽

pp. 27-1-27-14

Author(s):

Victor Zyuban ◽

Philip Strenski

Keyword(s):

Power Performance ◽

Trade Offs

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Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes

Lecture Notes in Computer Science - High Performance Computing ◽

10.1007/978-3-540-39707-6_9 ◽

2003 ◽

pp. 113-126 ◽

Cited By ~ 1

Author(s):

Miquel Pericás ◽

Eduard Ayguadé ◽

Javier Zalamea ◽

Josep Llosa ◽

Mateo Valero

Keyword(s):

Power Performance ◽

Trade Offs

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Towards modeling vehicular networks with power-performance trade-offs

2017 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS) ◽

10.1109/ants.2017.8384181 ◽

2017 ◽

Author(s):

Sriram Sankaran ◽

Manish Gupta

Keyword(s):

Vehicular Networks ◽

Power Performance ◽

Trade Offs

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System-level power-performance trade-offs in bus matrix communication architecture synthesis

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176327 ◽

2006 ◽

Cited By ~ 21

Author(s):

Sudeep Pasricha ◽

Young-Hwan Park ◽

Fadi J. Kurdahi ◽

Nikil Dutt

Keyword(s):

System Level ◽

Power Performance ◽

Communication Architecture ◽

Trade Offs

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Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage

10.1109/date.2005.243 ◽

2005 ◽

Cited By ~ 2

Author(s):

R. Bai ◽

Nam-Sung Kim ◽

Tae Ho Kgil ◽

D. Sylvester ◽

T. Mudge

Keyword(s):

Nanometer Scale ◽

Power Performance ◽

Trade Offs ◽

Total Leakage ◽

Multi Level

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Energy-efficient data centres : model-based analysis of power-performance trade-offs

10.3990/1.9789036546881 ◽

2018 ◽

Author(s):

Björn Frits Postema

Keyword(s):

Energy Efficient ◽

Power Performance ◽

Model Based ◽

Trade Offs ◽

Efficient Data ◽

Data Centres ◽

Model Based Analysis

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Power/Performance Trade-offs for Direct Networks

Parallel Computer Routing and Communication - Lecture Notes in Computer Science ◽

10.1007/3-540-69352-1_20 ◽

1998 ◽

pp. 231-244 ◽

Cited By ~ 2

Author(s):

Chirag S. Patel ◽

Sek M. Chai ◽

Sudhakar Yalamanchili ◽

David E. Schimmel

Keyword(s):

Power Performance ◽

Trade Offs ◽

Direct Networks

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Power-performance trade-offs in IaaS cloud: A scalable analytic approach

2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W) ◽

10.1109/dsnw.2011.5958802 ◽

2011 ◽

Cited By ~ 17

Author(s):

Rahul Ghosh ◽

Vijay K. Naik ◽

Kishor S. Trivedi

Keyword(s):

Analytic Approach ◽

Power Performance ◽

Trade Offs

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Power-Performance Trade-Offs in Second Level Memory Used by an ARM-Like RISC Architecture

Power Aware Computing - Series in Computer Science ◽

10.1007/978-1-4757-6217-4_11 ◽

2002 ◽

pp. 211-224

Author(s):

Kiran Puttaswamy ◽

Lakshmi Narasimhan Chakrapani ◽

Kyu-Won Choi ◽

Yuvraj Singh Dhillon ◽

Utku Diril ◽

...

Keyword(s):

Power Performance ◽

Trade Offs

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