Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework

2006 ◽  
Author(s):  
F. Mehdipour ◽  
M.S. Zamani ◽  
H.R. Ahmadifar ◽  
M. Sedighi ◽  
K. Murakami
Keyword(s):  
Reconfigurable Computing ◽  
Physical Design ◽  
Design Framework ◽  
Computing Systems ◽  
Temporal Partitioning

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

Integration ◽  
2019 ◽  
Vol 65 ◽  
pp. 97-103 ◽  
Author(s):  
Yu-Fan Chiang ◽  
Wei-Yu Chien ◽  
Yue-Der Chih ◽  
Jonathan Chang ◽  
Chrong Jung Lin ◽  
...  
Keyword(s):  
Reconfigurable Computing ◽  
Logic Gates ◽  
Computing Systems

scholarly journals Application of Multi Layer Artificial Neural Network in the Diagnosis System: A Systematic Review

2018 ◽  
Vol 7 (3) ◽  
pp. 138
Author(s):  
Arvind Singh Rawat ◽  
Arti Rana ◽  
Adesh Kumar ◽  
Ashish Bagwari
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Reconfigurable Computing ◽  
Research Papers ◽  
Computing Systems ◽  
System A ◽  
Major Scale ◽  
Artificial Neural ◽  
Artificial Neural Network Ann ◽  
Execution Technique

Basic hardware comprehension of an artificial neural network (ANN), to a major scale depends on the proficientrealization of a distinctneuron. For hardware execution of NNs, mostly FPGA-designed reconfigurable computing systems are favorable .FPGA comprehension of ANNs through a hugeamount of neurons is mainlyan exigentassignment. This workconverses the reviews on various research articles of neural networks whose concernsfocused in execution of more than one input neuron and multilayer with or without linearity property by using FPGA. An execution technique through reserve substitution isprojected to adjust signed decimal facts. A detailed review of many research papers have been done for the <br /> proposed work.

scholarly journals Haiwan dan Ternakan dalam Quran: Statistik dan Objektif Penyebutan

2020 ◽  
Vol 16 (2) ◽  
pp. 69-89
Author(s):  
Adnan Mohamed Yusoff ◽  
Abdoul Karim Toure
Keyword(s):  
Natural Resources ◽  
Human Life ◽  
Physical Design ◽  
Point Of View ◽  
Basic Data ◽  
Design Framework ◽  
Scientific Journals ◽  
Statistical Point ◽  
Actual Form ◽  
The Way

Animals and livestock are part of the main phenomenon of the Quran which highlights its intimacy with nature and human life. Names, types, properties, stories or matters that are related to animals and livestock appear specifically, scientifically and strategically in the Quran. This phenomenon attracts researchers to observe this emerging trend from a statistical point of view including the type of animal, frequency and place of emergence, as well as the objective of its mention either in actual form or as a metaphor. Thus, this study aims to identify the name or type of animal that has been selected to be immortalised in this Holy Book, the frequency and condition of its appearance, and subsequently the objective of its mention in the verse or surah. This is very important as basic data which will pave the way to a more advanced study in highlighting the majesty and miracles of the Quran in various dimensions that are related to natural resources. Correspondingly, this is a library study that is based on research on the text, especially the books of authentic interpretation, contemporary tafsir studies, the Ulum Quran, scientific journals, and other related texts. Among the important findings of the study is that animals and livestock are not a side element that comes to complete the beauty of the Quranic word or metaphor, or the physical design framework of its arrangement alone, for the presence of each of these animals or livestock is to carry the mission and certain objectives that cannot be played by other components in it. This study also paves the way for various further studies that can be explored by interested researchers, as well as in tadabbur activities that successfully attract the interest of today's society to get closer to the Quran.

scholarly journals A Graph-based Design Framework for Global Computing Systems

2009 ◽  
Vol 236 ◽  
pp. 117-130 ◽  
Author(s):  
Antonio Bucchiarone ◽  
Greg Dennis ◽  
Stefania Gnesi
Keyword(s):  
Design Framework ◽  
Computing Systems ◽  
Global Computing

THE PARALLEL-PIPELINED IMPLEMENTATION OF THE FRACTAL IMAGE COMPRESSION FOR RECONFIGURABLE COMPUTING SYSTEMS

2021 ◽  
pp. 37-44
Author(s):  
I. I. Levin ◽  
M. D. Chekina
Keyword(s):  
Image Compression ◽  
Reconfigurable Computing ◽  
Fractal Image Compression ◽  
Computing Systems ◽  
Image Encoding ◽  
Fractal Image ◽  
Computational Structure ◽  
Parallel Pipeline ◽  
Performance Reduction ◽  
Critical Resource

The developed fractal image compression method, implemented for reconfigurable computing systems is described. The main idea parallel fractal image compression based on parallel execution pairwise comparison of domain and rank blocks. Achievement high performance occurs at the expense of simultaneously comparing maximum number of pairs. Implementation fractal image compression for reconfigurable computing systems has two critical resources, as number of input channels and FPGA Look-up Table (LUT). The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel, preliminarily produced performance reduction parallel computational structure. The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel computations organiation. For using parallel-pipeline computations organization, preliminarily have produce performance reduction parallel computational structure. Each operator has routed to computational structure sequentially (bit by bit) to save computational resources and reduces equipment downtime. Storing iterated functions system coefficients for image encoding has been introduced in data structure, which correlates between corresponding parameters the numbers of rank and domain blocks. Applying this approach for parallel-pipeline programs allows scaling computing structure to plurality programmable logic arrays (FPGAs). Task implementation on the reconfigurable computer system Tertius-2 containing eight FPGAs 15 000 times provides performed acceleration relatively with universal multi-core processor, and 18 – 25 times whit to existing solutions for FPGAs.

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