MegaProto: A Low-Power and Compact Cluster for High-Performance Computing

2005 ◽  
Author(s):  
H. Nakashima ◽  
H. Nakamura ◽  
M. Sato ◽  
T. Boku ◽  
S. Matsuoka ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance Computing ◽  
High Performance ◽  
Performance Computing ◽  
Compact Cluster

scholarly journals Programming the Adapteva Epiphany 64-core network-on-chip coprocessor

2015 ◽  
Vol 31 (4) ◽  
pp. 285-302 ◽  
Author(s):  
Anish Varghese ◽  
Bob Edwards ◽  
Gaurav Mitra ◽  
Alistair P Rendell
Keyword(s):  
Low Power ◽  
High Performance Computing ◽  
High Performance ◽  
Large Scale ◽  
Matrix Multiplication ◽  
Building Blocks ◽  
Mesh Network ◽  
Peak Performance ◽  
Core Network ◽  
Performance Computing

Energy efficiency is the primary impediment in the path to exascale computing. Consequently, the high-performance computing community is increasingly interested in low-power high-performance embedded systems as building blocks for large-scale high-performance systems. The Adapteva Epiphany architecture integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of theoretical performance. However, with just 32 KB of memory per eCore for storing both data and code, programming the Epiphany system presents significant challenges. In this paper we evaluate the performance of a 64-core Epiphany system with a variety of basic compute and communication micro-benchmarks. Further, we implemented two well known application kernels, 5-point star-shaped heat stencil with a peak performance of 65.2 GFLOPS and matrix multiplication with 65.3 GFLOPS in single precision across 64 Epiphany cores. We discuss strategies for implementing high-performance computing application kernels on such memory constrained low-power devices and compare the Epiphany with competing low-power systems. With future Epiphany revisions expected to house thousands of cores on a single chip, understanding the merits of such an architecture is of prime importance to the exascale initiative.

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