A high performance,low complexity algorithm for compile-time task scheduling in heterogeneous systems

2004 ◽  
Author(s):  
T. Hagras ◽  
J. Janecek
Keyword(s):  
Task Scheduling ◽  
High Performance ◽  
Heterogeneous Systems ◽  
Low Complexity ◽  
Time Task ◽  
Complexity Algorithm

A Study for VM Placement Schemes in Cloud

2017 ◽  
Vol 7 (8) ◽  
pp. 208
Author(s):  
Ramandeep Kaur ◽  
Navpreet Kaur
Keyword(s):  
Cloud Computing ◽  
Reaction Time ◽  
Task Scheduling ◽  
Specific Time ◽  
Due Date ◽  
Vm Placement ◽  
Time Task ◽  
Wide Range ◽  
The Web

The cloud computing can be essentially expressed as aconveyance of computing condition where distinctive assets are conveyed as a support of the client or different occupants over the web. The task scheduling basically concentrates on improving the productive use of assets and henceforth decrease in task fruition time. Task scheduling is utilized to allot certain tasks to specific assets at a specific time occurrence. A wide range of systems has been exhibited to take care of the issues of scheduling of various tasks. Task scheduling enhances the productive use of asset and yields less reaction time with the goal that the execution of submitted tasks happens inside a conceivable least time. This paper talks about the investigation of need, length and due date based task scheduling calculations utilized as a part of cloud computing.

A Low Complexity Algorithm to Improve Data Rates in LTE MBMS Systems.

2015 ◽  
Vol 4 (1) ◽  
pp. 25-29
Author(s):  
Vidyapogula Naveen ◽  
◽  
S. Thulasi Prasad ◽  
Keyword(s):  
Low Complexity ◽  
Data Rates ◽  
Complexity Algorithm

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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