Error detection and correction of single event upset (SEU) tolerant latch

Error Detection and Correction On-Board Nanosatellites Using Hamming Codes

Journal of Electrical and Computer Engineering ◽

10.1155/2019/3905094 ◽

2019 ◽

Vol 2019 ◽

pp. 1-15 ◽

Cited By ~ 3

Author(s):

Caleb Hillier ◽

Vipin Balyan

Keyword(s):

Error Correction ◽

Error Detection ◽

Simulation Software ◽

Hamming Code ◽

Single Event ◽

Hamming Codes ◽

Single Event Effects ◽

Effective Version ◽

Fast Speed ◽

Error Detection And Correction

The field of nanosatellites is constantly evolving and growing at a very fast speed. This creates a growing demand for more advanced and reliable EDAC systems that are capable of protecting all memory aspects of satellites. The Hamming code was identified as a suitable EDAC scheme for the prevention of single event effects on-board a nanosatellite in LEO. In this paper, three variations of Hamming codes are tested both in Matlab and VHDL. The most effective version was Hamming [16, 11, 4]2. This code guarantees single-error correction and double-error detection. All developed Hamming codes are suited for FPGA implementation, for which they are tested thoroughly using simulation software and optimized.

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An Error Correction Code for Use in Space Vehicle Computers

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.121-126.3784 ◽

2011 ◽

Vol 121-126 ◽

pp. 3784-3788

Author(s):

R.N. Huang ◽

B. Gong ◽

Yun Jiang Lou

Keyword(s):

Error Correction ◽

Error Detection ◽

Efficient Solution ◽

Space Vehicle ◽

Space Vehicles ◽

Memory Cells ◽

Hamming Code ◽

Single Event Upset ◽

Single Event ◽

Signal Error

Memory cells of space vehicle computers generate errors in their stored data because of radiation. The main reason of the error is single event upset (SEU). Hamming code which has Capability of correcting one bit and detecting two bits is usually used in space vehicles to secure the memory data. As the density of the memory is more and more high, the possibility of multiple bits upset (MBU) increase and hamming code may be inadequate. In this paper, a (15,8) code is presented which can correct all double-adjacent errors and triple-adjacent errors in addition to signal error correction (SEC) and double error detection (DED). It is a powerful and efficient solution to SEU and MBU.

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Characterization of Single Event Cell Upsets in a Radiation Hardened SRAM in a 40 nm Bulk CMOS Technology

Electronics ◽

10.3390/electronics9060927 ◽

2020 ◽

Vol 9 (6) ◽

pp. 927

Author(s):

Guoqing Yang ◽

Junting Yu ◽

Jincheng Zhang ◽

Xiangyuan Liu ◽

Qiang Chen

Keyword(s):

Integrated Circuits ◽

Single Cell ◽

Error Detection ◽

Random Access ◽

Cmos Technology ◽

Single Event ◽

Close Spacing ◽

Error Detection And Correction ◽

Radiation Hardened ◽

Multiple Cell

A large amount of data needs to be stored in integrated circuits when data are being processed. The integrated circuits contain a large amount of static random access memory (SRAM) due to its high level of integration and speed. SRAM units should be as small as possible to achieve higher storage density. In this work, the features of single cell upsets (SCUs) and multiple cell upsets (MCUs) in a full custom SRAM are tested for a 40 nm bulk CMOS technology node, and Ge (linear energy transfer (LET) = 37.3 MeV cm2/mg), Cl (LET = 13.1 MeV cm2/mg), Al (LET = 8.6 MeV cm2/mg), O (LET = 3.1 MeV cm2/mg), and Li (LET = 0.5 MeV cm2/mg) particles are used. The test results show that the total single cell upset events are 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively. Moreover, due to single event upset reversal mechanism, multiple cell upsets significantly decrease. The total multiple cell upset events are 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively. There are a lot of single cell upsets appearing under Ge, Cl, Al, O, and Li exposure. The number is increasing with increasing LET, which means that well contacts still need optimization in the full custom SRAM. Close spacing of well contacts or increasing contacts are the approaches used to drain the excess carriers quickly, and error detection and correction (EDAC) is used for SRAM technology. The features show that SCUs have become a major source of soft errors for the full custom SRAM. Combining close spacing of well contacts with error detection and correction (EDAC) and a well engineering scheme are used to reduce single cell upsets, although there are a few MCUs which are inevitable. Radiation hardened by design schemes needs to be further improved.

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