Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics

Author(s):  
Partha Pratim Pande ◽  
Amlan Gangul ◽  
Brett Feero ◽  
Cristian Grecu
2001 ◽  
Vol 13 (4) ◽  
pp. 799-815 ◽  
Author(s):  
Vijay Balasubramanian ◽  
Don Kimber ◽  
Michael J. Berry II

Energy-efficient information transmission may be relevant to biological sensory signal processing as well as to low-power electronic devices. We explore its consequences in two different regimes. In an “immediate” regime, we argue that the information rate should be maximized subject to a power constraint, and in an “exploratory” regime, the transmission rate per power cost should be maximized. In the absence of noise, discrete inputs are optimally encoded into Boltzmann distributed output symbols. In the exploratory regime, the partition function of this distribution is numerically equal to 1. The structure of the optimal code is strongly affected by noise in the transmission channel. The Arimoto-Blahut algorithm, generalized for cost constraints, can be used to derive and interpret the distribution of symbols for optimal energy-efficient coding in the presence of noise. We outline the possibilities and problems in extending our results to information coding and transmission in neurobiological systems.


2017 ◽  
Vol 26 (05) ◽  
pp. 1750084 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma

An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90[Formula: see text]nm technology operating at 1.2[Formula: see text]V supply voltage and UMC 55[Formula: see text]nm CMOS technology operating at 1.0[Formula: see text]V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.


Author(s):  
Mainak Adhikari ◽  
Debapriya Roy

Green computing considers use of computers and related resources in an eco-friendly manner such as the implementation of energy efficiency in Servers, Peripherals etc. In recent years, companies in the computer industry realize that going green is in their best interest, both in terms of public relations and reduced costs. The principle behind energy efficient coding is to save power by getting software to make less use of the hardware, rather than continuing to run the same code on hardware that uses less power. This chapter first discuss features, challenges and impacts of green computing. Finally this chapter point out the standard and recommendation of green computing with suitable example.


2007 ◽  
Vol 16 (06) ◽  
pp. 929-942
Author(s):  
J. V. R. RAVINDRA ◽  
M. B. SRINIVAS

In the current era of deep-submicron technology (DSM), minimizing the propagation delay and energy consumption on buses is the most important design objective in system-on-chip (SOC) designs. In particular, coupling effects between wires on the bus can cause serious problems such as cross-talk delay, noise, and power dissipation. Most of the work reported in literature so far concentrates on either minimizing the energy consumption or the delay. In this paper, the authors propose two coding techniques for achieving energy and delay efficiency in data transmission on on-chip buses. It is shown, using SPEC 2000 benchmark suit, that the proposed techniques achieve an energy saving of 35% or over the un-encoded data on the data bus and eliminate cross-talk-delay classes 6, 5, and 4.


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