VLSI design optimization of input/output-buffered broadband ATM switches

2002 ◽  
Author(s):  
Hong Shi ◽  
C. Zukowski ◽  
O. Wing
Keyword(s):  
Design Optimization ◽  
Vlsi Design ◽  
Input Output ◽  
Atm Switches

Speedup and buffer division in input/output queuing atm switches

2003 ◽  
Vol 51 (7) ◽  
pp. 1195-1203 ◽  
Author(s):  
Jiang Xie ◽  
Chin-Tau Lea
Keyword(s):  
Input Output ◽  
Atm Switches

scholarly journals VLSI Design of A Chip With High Speed Atm Switch-A Review

2021 ◽  
Vol 12 (2) ◽  
pp. 1655-1659
Author(s):  
Vishal Chandra , Et. al.
Keyword(s):  
High Speed ◽  
Video Conferencing ◽  
Asynchronous Transfer Mode ◽  
Vlsi Design ◽  
Input Output ◽  
Computer Communication ◽  
Atm Switch ◽  
Transfer Mode ◽  
Computer Communication Network ◽  
The Postponement

In current computer communication network, it is overwhelmed by two technologies, in particular Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Association situated ATM is the awesome constant administrations which require ensured nature of-administration like video conferencing. Be that as it may, connectionless IP is more proficient than ATM for non-ongoing administrations like email. Right now, the significant exploration challenge is on the most proficient method to coordinate ATM and IP into a solitary network effectively. It is shown by the acknowledgment of the highlight of the A/I Net architecture: the A/I Switch. In this postulation, a VLSI execution of a multistage self-steering ATM switch texture which is one of the vital parts of the A/I Switch will be presented. The size of the switch model is 16x16. The chip is intended to work at the very least frequency of 100MHz and the framework is equipped for dealing with the OC-12 (622 Mbps) connect rate. In view of a piece cut architecture, the whole 16x16 switch is acknowledged utilizing four indistinguishable chips. It accomplishes elite by using dispersed control and accelerate with the input-output buffering technique. A need structure, which upholds four-level, permits the postponement delicate ATM cells to be switched with the briefest inertness. It likewise empowers the non-interleaving directing plan of IP cells.

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