System on chip implementation of 1-D wavelet transform based denoising of fiber optic gyroscope signal on FPGA

Author(s):  
Samrat L. Sabat ◽  
P. Rangababu ◽  
K. P. Karthik ◽  
G. Krishhnaprasad ◽  
J. Nayak
2020 ◽  
Vol 41 (Supplement_1) ◽  
Author(s):  
Y W Hau ◽  
H W Lim ◽  
C W Lim ◽  
S Kasim

Abstract Stroke is one of the most severe cardiovascular disease which can potentially cause permanent disability. Atrial Fibrillation (AF) is one of the major risk factors of stroke that can be detected from electrocardiogram (ECG) monitoring.  Objective This study proposed an AF detection algorithm based on stationary wavelet transform (SWT) and artificial neural network (ANN) for screening purpose. The algorithm is aimed for embedded System-on-Chip (SoC) technology deployment as a standalone AF classifier for community in rural area where the internet infrastructure may not well established. Methods After standard ECG signal pre-processing, SWT is applied to filtered ECG and produces 12 sets of primary features in time-frequency domain. The power spectral density (PSD) and log energy entropy (LogEn) were calculated from these 12 sets of primary features, to measure atrial activity fall in frequency range of 4 to 9 Hz, and the randomness of an ECG signal caused by AF, respectively. Finally, the ANN classifier recognizes the pattern of AF based on high atrial activity and randomness of ECG signal. Algorithm exploration is carried out to determine the optimum parameter value which can yield the best classification and suitable to be implemented in embedded SoC technology for real-time computation performance. ECG training and testing datasets of the proposed AF detection algorithm were extracted from MIT-BIH Atrial Fibrillation Database which consists of 23 ECG record with each record contains a 10 hours ECG data.  Results AF detection accuracy is 95.3% which was able to classify an ECG signal into categories of AF, sinus rhythm, and other arrhythmia.  Conclusion The proposed AF detection algorithm based on combination of SWT and ANN can achieve high accuracy and is suitable to be implemented as a standalone AF classifier based on embedded SoC technology targeted for early detection of AF in the community.


Author(s):  
Ш.С. Фахми ◽  
Н.В. Шаталова ◽  
В.В. Вислогузов ◽  
Е.В. Костикова

В данной работе предлагаются математический аппарат и архитектура многопроцессорной транспортной системы на кристалле (МПТСнК). Выполнена программно-аппаратная реализация интеллектуальной системы видеонаблюдения на базе технологии «система на кристалле» и с использованием аппаратного ускорителя известного метода формирования опорных векторов. Архитектура включает в себя сложно-функциональные блоки анализа видеоинформации на базе параллельных алгоритмов нахождения опорных точек изображений и множества элементарных процессоров для выполнения сложных вычислительных процедур алгоритмов анализа с использованием средств проектирования на базе реконфигурируемой системы на кристалле, позволяющей оценить количество аппаратных ресурсов. Предлагаемая архитектура МПТСнК позволяет ускорить обработку и анализ видеоинформации при решении задач обнаружения и распознавания чрезвычайных ситуаций и подозрительных поведений. In this paper, we propose the mathematical apparatus and architecture of a multiprocessor transport system on a chip (MPTSoC). Software and hardware implementation of an intelligent video surveillance system based on the "system on chip" technology and using a hardware accelerator of the well-known method of forming reference vectors. The architecture includes complex functional blocks for analyzing video information based on parallel algorithms for finding image reference points and a set of elementary processors for performing complex computational procedures for algorithmic analysis. using design tools based on a reconfigurable system on chip that allows you to estimate the amount of hardware resources. The proposed MPTSoC architecture makes it possible to speed up the processing and analysis of video information when solving problems of detecting and recognizing emergencies and suspicious behaviors


2020 ◽  
Vol 96 (3s) ◽  
pp. 89-96
Author(s):  
А.А. Беляев ◽  
Я.Я. Петричкович ◽  
Т.В. Солохина ◽  
И.А. Беляев

Рассмотрены особенности архитектуры и основные характеристики аппаратного видеокодека по стандарту H.264, входящего в состав микросхемы 1892ВМ14Я (MCom-02). Описан механизм синхронизации потоков данных на основе набора флагов событий. Приведены экспериментальные результаты измерения характеристик производительности разработанного видеокодека на реальных видеосюжетах при различных форматах передаваемого изображения. The paper considers main architectural features and characteristics of H.264 hardware video codec IP-core as a part of MCom- 02 system-on-chip (SoC). Bedides, it presents data flow synchronization mechanism based on event flags set, as well as experimental results of performance measurements for the designed video codec IP-core obtained for different video sequences and different image formats.


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