A new hardware architecture for H.264 intra prediction frame processing

2011 ◽  
Author(s):  
Xu Shou-Gen ◽  
Wang Ming-Jiang ◽  
Zuo Shi-Kai
Keyword(s):  
Intra Prediction ◽  
Hardware Architecture ◽  
Frame Processing

scholarly journals An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder

ETRI Journal ◽  
2005 ◽  
Vol 27 (5) ◽  
pp. 511-524 ◽  
Author(s):  
Kibum Suh ◽  
Seongmo Park ◽  
Hanjin Cho
Keyword(s):  
Intra Prediction ◽  
Hardware Architecture

Hardware architecture for H.264/AVC intra 16×16 frame processing

2009 ◽  
Author(s):  
H. Loukil ◽  
S. Arous ◽  
I. Werda ◽  
A. Ben Atitallah ◽  
P. Kadionik ◽  
...  
Keyword(s):  
Hardware Architecture ◽  
Frame Processing

scholarly journals FPGA-based implementation of intra prediction module for HEVC decoder

2019 ◽  
Vol 8 (2) ◽  
pp. 6130-6137
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Cmos Technology ◽  
Intra Prediction ◽  
Hardware Architecture ◽  
Video Frame ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Prediction Module ◽  
Block Sizes

The High Efficiency Video Coding (HEVC) is the new standard which is designed to support High Definition (HD) and Ultra-HD video cotenants. In HEVC, several new coding tools are adopted in order to improve the coding efficiency and compression ratio but with a significant increase in the computational complexity comparing to the previous standard H.264/AVC. In this paper, we focus on reducing the complexity of the most consuming block in the HEVC decoder standard which is the intra prediction module. In this context, we propose an optimized hardware architecture dedicated to support the 34 modes of intra prediction module considering 4×4, 8×8 and 16×16 block sizes. The proposed design exploits the symmetric property between horizontal and vertical modes. Hence, we implement a new hardware architecture that factorizes the same hardware resources for both directions which leads to save the hardware cost, the power consumption and the processing time. Furthermore, the different block sizes are implemented independently in order to avoid memory overhead while accessing to the shared memory. The implemented design using Xilinx Zynq-based FPGA platform can process in real time the Ultra-HD video frame of resolution (4096×2048) at 232 MHz. As well, the synthesis results using the TSMC 180 nm CMOS technology provide similar performance than our FPGA implementation. Finally, the HW/SW implementation of full HEVC decoder can process the decoding of 15 FPS in best case for 240p video resolution with a gain of 60% in power consumption.

An Optimized Hardware Architecture of 4×4 Intra Prediction for HEVC Standard

2018 ◽  
pp. 127-144
Author(s):  
M. Kammoun ◽  
A. Ben Atitallah ◽  
H. Loukil ◽  
N. Masmoudi
Keyword(s):  
Intra Prediction ◽  
Hardware Architecture
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