Research on Real-Time Video Stitching Based on SURB Algorithm

2017 ◽  
Author(s):  
Aiguo Li ◽  
Rui Wang ◽  
Shuai Zhou
Keyword(s):  
Real Time ◽  
Video Stitching

scholarly journals A Real-Time Video Stitching Algorithm in H.264/AVC Compressed Domain

2014 ◽  
Vol 39C (6) ◽  
pp. 503-511 ◽  
Author(s):  
Ganzorig Gankhuyag ◽  
Eun Gi Hong ◽  
Giyeol Kim ◽  
Younghwan Kim ◽  
Yoonsik Choe
Keyword(s):  
Real Time ◽  
Compressed Domain ◽  
Video Stitching

FPGA-based real time video stitching method for video surveillance

Optik ◽  
2015 ◽  
Vol 126 (21) ◽  
pp. 2804-2808 ◽  
Author(s):  
Xiaoqing Yin ◽  
Weili Li ◽  
Yu Liu ◽  
Bin Wang ◽  
Maojun Zhang
Keyword(s):  
Real Time ◽  
Video Surveillance ◽  
Video Stitching

An Effective Multi-Camera Dataset and Hybrid Feature Matcher for Real-Time Video Stitching

2021 ◽  
Author(s):  
Md Imran Hosen ◽  
Md Baharul Islam ◽  
Arezoo Sadeghzadeh
Keyword(s):  
Real Time ◽  
Video Stitching

scholarly journals A fast and robust real-time surveillance video stitching method

2020 ◽  
Vol 1651 ◽  
pp. 012170
Author(s):  
Tao Yang ◽  
Fenlin Jin ◽  
Jianxin Luo
Keyword(s):  
Real Time ◽  
Surveillance Video ◽  
Video Stitching

scholarly journals REAL TIME VIDEO STITCHING IMPLEMENTATION ON A ZYNQ FPGA SOC

2021 ◽  
Author(s):  
Dhimiter Qendri
Keyword(s):  
Real Time ◽  
Imaging System ◽  
Vision System ◽  
Processing System ◽  
Video Stream ◽  
Panoramic Imaging ◽  
Vision Processing ◽  
Video Stitching ◽  
Panoramic Video ◽  
Set Up

This project details the design and implementation of an image processing pipeline that targets real time video-stitching for semi-panoramic video synthesis. The scope of the project includes the analysis of possible approaches, selection of processing algorithms and procedures, design of experimental hardware set-up (including the schematic capture design of a custom catadioptric panoramic imaging system) and firmware/software development of the vision processing system components. The goal of the project is to develop a frame-stitching IP module as well as an efficient video registration algorithm capable for synthesis of a semi-panoramic video-stream at 30 frames-per-second (fps) rate with minimal FPGA resource utilization. The developed components have been validated in hardware. Finally, a number of hybrid architectures that make use of the synergy between the CPU and FPGA section of the ZYNQ SoC have been investigated and prototyped as alternatives to a complete hardware solution. Keyword: Video stitching, Panoramic vision, FPGA, SoC, vision system, registration

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