Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective

2006 ◽  
Author(s):  
Calin Ciordas ◽  
Kees Goossens ◽  
Twan Basten ◽  
Andrei Radulescu ◽  
Andre Boon
Keyword(s):  
Time Perspective ◽  
Networks On Chip ◽  
Run Time ◽  
On Chip

scholarly journals Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip

2011 ◽  
pp. 232-247 ◽  
Author(s):  
Xiaohang Wang ◽  
Maurizio Palesi ◽  
Mei Yang ◽  
Yingtao Jiang ◽  
Michael C. Huang ◽  
...  
Keyword(s):  
Networks On Chip ◽  
Run Time ◽  
On Chip

scholarly journals Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

2013 ◽  
Vol 28 (1) ◽  
pp. 54-71 ◽  
Author(s):  
Xiao-Hang Wang ◽  
Peng Liu ◽  
Mei Yang ◽  
Maurizio Palesi ◽  
Ying-Tao Jiang ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Networks On Chip ◽  
Run Time ◽  
On Chip

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

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