Effect of Source-Connected Field Plate on Electric Field Distribution and Breakdown Voltage in AlGaN/GaN HEMTs

2006 ◽  
Author(s):  
Sheng-hui Lu ◽  
Wei Zhou ◽  
Di Yan ◽  
Jian-xin Xia ◽  
Mo-hua Yang
Keyword(s):  
Electric Field ◽  
Field Distribution ◽  
Breakdown Voltage ◽  
Electric Field Distribution ◽  
Field Plate ◽  
Gan Hemts

scholarly journals Simulation of AlGaN/GaN HEMTs’ Breakdown Voltage Enhancement Using Gate Field-Plate, Source Field-Plate and Drain Field Plate

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 406 ◽  
Author(s):  
Biyan Liao ◽  
Quanbin Zhou ◽  
Jian Qin ◽  
Hong Wang
Keyword(s):  
Electric Field ◽  
Breakdown Voltage ◽  
Structural Parameters ◽  
High Electron Mobility Transistors ◽  
High Electron ◽  
Insulator Layer ◽  
Field Plate ◽  
2D Simulation ◽  
Gan Hemts ◽  
Drain Field

A 2-D simulation of off-state breakdown voltage (VBD) for AlGaN/GaN high electron mobility transistors (HEMTs) with multi field-plates (FPs) is presented in this paper. The effect of geometrical variables of FP and insulator layer on electric field distribution and VBD are investigated systematically. The FPs can modulate the potential lines and distribution of an electric field, and the insulator layer would influence the modulation effect of FPs. In addition, we designed a structure of HEMT which simultaneously contains gate FP, source FP and drain FP. It is found that the VBD of AlGaN/GaN HEMTs can be improved greatly with the corporation of gate FP, source FP and drain FP. We achieved the highest VBD in the HEMT contained with three FPs by optimizing the structural parameters including length of FPs, thickness of FPs, and insulator layer. For HEMT with three FPs, FP-S alleviates the concentration of the electric field more effectively. When the length of the source FP is 24 μm and the insulator thickness between the FP-S and the AlGaN surface is 1950 nm, corresponding to the average electric field of about 3 MV/cm at the channel, VBD reaches 2200 V. More importantly, the 2D simulation model is based on a real HMET device and will provide guidance for the design of a practical device.

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

2012 ◽  
Vol 21 (7) ◽  
pp. 078502 ◽  
Author(s):  
Xia-Rong Hu ◽  
Bo Zhang ◽  
Xiao-Rong Luo ◽  
Yuan-Gang Wang ◽  
Tian-Fei Lei ◽  
...  
Keyword(s):  
Electric Field ◽  
Analytical Model ◽  
Field Distribution ◽  
Breakdown Voltage ◽  
Electric Field Distribution ◽  
Surface Electric Field

Area-Optimized JTE for 4.5 kV Non Ion-Implanted 4H-SiC BJT

2013 ◽  
Vol 740-742 ◽  
pp. 974-977 ◽  
Author(s):  
Arash Salemi ◽  
Hossein Elahipanah ◽  
Benedetto Buono ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
Electric Field ◽  
Ion Implantation ◽  
Field Distribution ◽  
Breakdown Voltage ◽  
Contact Area ◽  
Electric Field Distribution ◽  
Current Gain ◽  
High Current ◽  
High Breakdown Voltage ◽  
Base Contact

Non ion-implantation mesa etched 4H-SiC BJT with three-zone JTE of optimized lengths and doses (descending sequences) has been simulated. This design presents an efficient electric field distribution along the device. The device area has been optimized and considerably reduced. As a result of this comprehensive optimization, a high breakdown voltage and high current gain have been achieved; meanwhile the device area with a constant emitter and base contact area has been reduced by about 30%.

Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes

2018 ◽  
Vol 27 (03n04) ◽  
pp. 1840018
Author(s):  
Mst Shamim Ara Shawkat ◽  
Mohammad Habib Ullah Habib ◽  
Md Sakib Hasan ◽  
Mohammad Aminul Haque ◽  
Nicole McFarlane
Keyword(s):  
Electric Field ◽  
Field Distribution ◽  
Breakdown Voltage ◽  
Gate Voltage ◽  
Electric Field Distribution ◽  
Device Simulation ◽  
Deep Submicron ◽  
Uniform Electric Field ◽  
Cmos Process ◽  
Submicron Process

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

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