Development of frequency variable inverter based on SOPC and Nios II

2012 ◽  
Author(s):  
He-Jin Liu ◽  
Ke-Jun Li ◽  
Wei-Jen Lee ◽  
Hong-Xia Gao ◽  
Ying Sun
Keyword(s):  
Nios Ii

Performance of DSP operations implemented using a soft microprocessor: a case study based on Nios II

2021 ◽  
Author(s):  
Aleieldin Shamseldin ◽  
Hassan Soubra ◽  
Reham ElNabawy
Keyword(s):  
Nios Ii

Digital Image Encryption Test System Based on FPGA and Nios II Soft Core

2021 ◽  
Vol 55 (5) ◽  
pp. 490-499
Author(s):  
Zhong-xun Wang ◽  
Kai-yue Sha ◽  
Xing-long Gao
Keyword(s):  
Image Encryption ◽  
Digital Image ◽  
Test System ◽  
Soft Core ◽  
Nios Ii ◽  
Digital Image Encryption

scholarly journals Implementation of a camera system using nios II on the altera DE2-70 board

2019 ◽  
Vol 14 (2) ◽  
pp. 513
Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek
Keyword(s):  
Video Processing ◽  
Random Access ◽  
Camera System ◽  
Embedded Processor ◽  
Nios Ii ◽  
Development Platform ◽  
Quartus Ii ◽  
Field Programmable ◽  
Sdram Controller ◽  
Recorded Image

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.

Design of GTAW Wire Feeder Control System Based on Nios II

2013 ◽  
Vol 397-400 ◽  
pp. 1909-1912 ◽  
Author(s):  
Fu Yang ◽  
Shu Zhang ◽  
Wen Ming Zhang
Keyword(s):  
Control System ◽  
Digital Control ◽  
Embedded Processor ◽  
Control Module ◽  
Nios Ii ◽  
Gas Tungsten Arc ◽  
Welding Arc ◽  
Current Parameter ◽  
Wire Feeding ◽  
Feeding Control

Based on Nios II embedded processor control module, a digital control system was designed for wire feeding control of gas tungsten arc welding(GTAW). In the control system FPGA wave module is used to control the movement of the DC servo motor, and the digital control of pulsed wire feeder for GTAW was achieved. One and the same control module with Nios II embedded processor is used to control the wire feeder and the welding power source. Thus, the current parameter of pulsed welding arc can be obtained and used directly for controlling the speed of wire feeding. At last, the experiment results are provided to verify the validity.

scholarly journals Multi-Softcore Architecture on FPGA

2014 ◽  
Vol 2014 ◽  
pp. 1-13 ◽  
Author(s):  
Mouna Baklouti ◽  
Mohamed Abid
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Matrix Multiplication ◽  
Rapid Prototype ◽  
General Purpose ◽  
Parallel Applications ◽  
Multicore Systems ◽  
Processor Core ◽  
Nios Ii ◽  
Wide Range

To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs) are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication).

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