PARADIGM: an architecture for distributed vision processing

Real-time communication for distributed vision processing based on imprecise computation model

Proceedings 16th International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2002.1016513 ◽

2002 ◽

Cited By ~ 3

Author(s):

H. Yoshimoto ◽

D. Arita ◽

R.-I. Taniguchi

Keyword(s):

Real Time ◽

Computation Model ◽

Vision Processing ◽

Imprecise Computation ◽

Distributed Vision

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Programmable 2D image filter for AER vision processing

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) ◽

10.1109/icecs.1999.812236 ◽

2003 ◽

Author(s):

T. Serrano-Gotarredona ◽

A.G. Andreou ◽

B. Linares-Barranco

Keyword(s):

Image Filter ◽

Vision Processing

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A Multichip Neuromorphic System for Spike-Based Visual Information Processing

Neural Computation ◽

10.1162/neco.2007.19.9.2281 ◽

2007 ◽

Vol 19 (9) ◽

pp. 2281-2300 ◽

Cited By ~ 48

Author(s):

R. Jacob Vogelstein ◽

Udayan Mallik ◽

Eugenio Culurciello ◽

Gert Cauwenberghs ◽

Ralph Etienne-Cummings

Keyword(s):

Visual Information ◽

Reversal Potential ◽

Multiple Components ◽

Vision Processing ◽

Look Up Table ◽

Neural Spike ◽

Vlsi System ◽

Silicon Neurons ◽

Neuromorphic System ◽

Synaptic Parameters

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 × 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

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