Resource Sharing in Networks-on-Chip of Large Many-core Embedded Systems

2009 ◽  
Author(s):  
Fadi N. Sibai
Keyword(s):  
Embedded Systems ◽  
Resource Sharing ◽  
Networks On Chip ◽  
On Chip ◽  
Many Core

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support

2013 ◽  
Author(s):  
Dexue Zhang ◽  
Xiaoyang Zeng ◽  
Zongyan Wang ◽  
Weike Wang ◽  
Xinhua Chen
Keyword(s):  
Networks On Chip ◽  
Virtual Platform ◽  
On Chip ◽  
Many Core

Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

2014 ◽  
pp. 150-179
Author(s):  
Haoyuan Ying ◽  
Klaus Hofmann ◽  
Thomas Hollstein
Keyword(s):  
Embedded Systems ◽  
Design Optimization ◽  
Optimization Methods ◽  
Design Methods ◽  
System Level ◽  
System Level Design ◽  
Level Design ◽  
On Chip ◽  
Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

Software Defined Networks-on-Chip for Multi/Many-Core Systems

2016 ◽  
Author(s):  
R. Sandoval-Arechiga ◽  
R. Parra-Michel ◽  
J. L. Vazquez-Avila ◽  
J. Flores-Troncoso ◽  
S. Ibarra-Delgado
Keyword(s):  
Software Defined Networks ◽  
Networks On Chip ◽  
On Chip ◽  
Many Core

scholarly journals Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip

2018 ◽  
Vol 68 ◽  
pp. 581-602 ◽  
Author(s):  
Md Farhadur Reza ◽  
Dan Zhao ◽  
Hongyi Wu ◽  
Magdy Bayoumi
Keyword(s):  
Networks On Chip ◽  
Core Networks ◽  
On Chip ◽  
Many Core

scholarly journals Algoritmo Kmeans para Mapeamento Estático de Processos em Redes-em-Chip

2014 ◽  
Author(s):  
Cíntia Avelar ◽  
Pedro Penna ◽  
Henrique Freitas
Keyword(s):  
Networks On Chip ◽  
On Chip ◽  
Many Core

Desempenho é um ponto crucial em arquiteturas many-core com networks-on-chip. Uma das alternativas para alcanç á-lo consiste em mapear processos nos núcleos de processamento de forma a minimizar o custo de comunicação global entre processos. Nesse contexto, esse trabalho propõe o algoritmo Kmeans como uma estratégia alternativa às heurísticas BRD e Guloso. Para determinados padrões de comunicação, os resultados de simulação apontaram que o Kmeans conduz a melhores mapeamentos que as outras estratégias, sendo portanto uma boa opção para o mapeamento de processos em arquiteturas many-core com networks-on-chip.

scholarly journals Avaliação de Desempenho de Redes-em-Chip Sem Fio Single-Hop com NAS Parallel Benchmarks

2013 ◽  
Author(s):  
Amanda Maria P. Amorim ◽  
Henrique C. Freitas
Keyword(s):  
Wireless Networks ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Network Simulator ◽  
Networks On Chip ◽  
On Chip ◽  
Many Core

Em arquiteturas tradicionais de redes-em-chip, há influência do fio que pode reduzir a escalabilidade, rendimento e eficiência. Redes-em-chip sem fio (Wireless Networks-on-Chip WiNoCs) são alternativas para fornecer comunicação entre núcleos de processadores many-core com alta largura de banda e baixo consumo de energia. Em aplicações paralelas há comunicações entre vários núcleos demandando um projeto de rede-em-chip eficiente. Portanto, o objetivo deste trabalho é projetar e avaliar uma arquitetura WiNoC single-hop usando cargas de trabalho paralelas. A metodologia é baseada em simulações através do simulador de rede NS-2 (Network Simulator) e aplicações do NAS Parallel Benchmarks (NPB). A arquitetura WiNoC é baseada na topologia mesh 2-D com tecnologia de rádio UWB (Ultra Wide Band). A transmissão entre núcleos é avaliada com base nas comunicações unicast (1:1 e N: 1) e broadcast (1: N e N: N). A arquitetura WiNoC Single-hop tem alto desempenho nas comunicação broadcast, alcançando no máximo 2,21 % de perda de pacotes. Nas comunicações unicast, a WiNoC single-hop tem alto desempenho atingindo no máximo 0,02 % de perda de pacotes e 0,2 ms de latência. A maior taxa de perda de pacotes e latência ocorrem nas comunicações N:1, devido a concorrência dos pacotes pelo nó destino. A WiNoC Single-hop alcançou até 63,12 J de consumo de energia. É possível concluir que a arquitetura WiNoC Single-hop apresenta alto desempenho, mas precisa de melhorias para reduzir o consumo de energia aumentando a sua eficiência.

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