A Coarse-Grained Dynamically Reconfigurable Processing Array (RPA) for Multimedia Application

2007 ◽  
Author(s):  
Guochang Zhou ◽  
Xubang Shen
Keyword(s):  
Multimedia Application ◽  
Coarse Grained ◽  
Dynamically Reconfigurable ◽  
Reconfigurable Processing

scholarly journals An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

2015 ◽  
Vol 17 (10) ◽  
pp. 1706-1720 ◽  
Author(s):  
Leibo Liu ◽  
Dong Wang ◽  
Min Zhu ◽  
Yansheng Wang ◽  
Shouyi Yin ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Coarse Grained ◽  
Processing Unit ◽  
Video Decoding ◽  
Reconfigurable Processing

scholarly journals Design Metrics in Quantum Turbulence Simulations: How Physics Influences Software Architecture

2004 ◽  
Vol 12 (3) ◽  
pp. 185-196 ◽  
Author(s):  
Damian W.I. Rouson ◽  
Yi Xiong
Keyword(s):  
Data Structures ◽  
Quantum Turbulence ◽  
Object Oriented Programming ◽  
Coarse Grained ◽  
Local Data ◽  
Design Metrics ◽  
Dynamically Reconfigurable ◽  
Fine Grained ◽  
Scientific Simulations ◽  
Global Operations

The information hiding philosophy of object-oriented programming encourages localizing data structures within objects rather than sharing data globally across different classes of objects. This emphasis on local data leads naturally to fine-grained data abstractions, particularly in scientific simulations involving large collections of small, discrete physical or mathematical objects. This paper focuses on a subset of such simulations where dynamically reconfigurable links bind the objects together. It is demonstrated that fine-grained data structures reduce the complexity of local operations on the data at the potential expense of increased global operation complexity. Two metrics are used to describe data structures: granularity is the number of instantiations required to cover the data space, whereas extent is the continuously traversable length of the data along a given direction. These definitions are applied to two abstractions for simulating the turbulent motion of quantum vortices in superfluid liquid helium. Several local and global operations on a fine-grained linked list are compared with those on a coarse-grained array. It is demonstrated that fine-grained data structures recover the simplicity of more coarse-grained structures if maximal extent is maintained as the granularity increases.

scholarly journals A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

2021 ◽  
Vol 11 (3) ◽  
pp. 32
Author(s):  
Hasan Irmak ◽  
Federico Corradi ◽  
Paul Detterer ◽  
Nikolaos Alachiotis ◽  
Daniel Ziener
Keyword(s):  
Neural Network ◽  
Reconfigurable Architecture ◽  
Frame Rate ◽  
Model Parameters ◽  
Hybrid Architecture ◽  
Throughput Performance ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Field Programmable ◽  
Reconfigurable Processing

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.

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