A New Method for FPGA-Based 24x24-Bit Low-Power Multiplier

2010 ◽  
Author(s):  
Jinpeng Xing ◽  
Chunfeng Xin ◽  
Zheying Li
Keyword(s):  
Low Power ◽  
New Method ◽  
Low Power Multiplier

scholarly journals A Low Power Multiplier using a 24-Transistor Latch Adder

2015 ◽  
Vol 8 (19) ◽  
Author(s):  
Savio Victor Gomes ◽  
P. Sasipriya ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
Low Power Multiplier

scholarly journals Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Full Adder ◽  
Double Pass ◽  
Voltage Level ◽  
Circuit Performance ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Implementation ◽  
Low Power Multiplier

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

Sign in / Sign up

Export Citation Format

Share Document