Coevolvable hardware platform for automatic hardware design of neural networks

2005 ◽  
Author(s):  
O. Hammami ◽  
K. Kuroda ◽  
Q. Zhao ◽  
K. Saito
Keyword(s):  
Neural Networks ◽  
Hardware Design ◽  
Hardware Platform

Hardware Design Automation of Convolutional Neural Networks

2016 ◽  
Author(s):  
Andrea Solazzo ◽  
Emanuele Del Sozzo ◽  
Irene De Rose ◽  
Matteo De Silvestri ◽  
Gianluca C. Durelli ◽  
...  
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Design Automation ◽  
Hardware Design

scholarly journals POETS: A Parallel Cluster Architecture for Spiking Neural Network

2021 ◽  
Vol 11 (4) ◽  
pp. 281-285
Author(s):  
Mahyar Shahsavari ◽  
◽  
Jonathan Beaumont ◽  
David Thomas ◽  
Andrew D. Brown
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Current System ◽  
Autonomous Control ◽  
Spiking Neural Networks ◽  
Spiking Neural Network ◽  
Hardware Platform ◽  
Cluster Architecture ◽  
Classification Pattern ◽  
Scalable Hardware

Spiking Neural Networks (SNNs) are known as a branch of neuromorphic computing and are currently used in neuroscience applications to understand and model the biological brain. SNNs could also potentially be used in many other application domains such as classification, pattern recognition, and autonomous control. This work presents a highly-scalable hardware platform called POETS, and uses it to implement SNN on a very large number of parallel and reconfigurable FPGA-based processors. The current system consists of 48 FPGAs, providing 3072 processing cores and 49152 threads. We use this hardware to implement up to four million neurons with one thousand synapses. Comparison to other similar platforms shows that the current POETS system is twenty times faster than the Brian simulator, and at least two times faster than SpiNNaker.

NEURAL NETWORKS IN ANALOG HARDWARE — DESIGN AND IMPLEMENTATION ISSUES

2000 ◽  
Vol 10 (01) ◽  
pp. 19-42 ◽  
Author(s):  
SORIN DRAGHICI
Keyword(s):  
Neural Networks ◽  
Power Consumption ◽  
Hardware Design ◽  
Chip Area ◽  
Design And Implementation ◽  
Trade Offs ◽  
Hardware Implementations ◽  
Noise Susceptibility

This paper presents a brief review of some analog hardware implementations of neural networks. Several criteria for the classification of general neural networks implementations are discussed and a taxonomy induced by these criteria is presented. The paper also discusses some characteristics of analog implementations as well as some trade-offs and issues identified in the work reviewed. Parameters such as precision, chip area, power consumption, speed and noise susceptibility are discussed in the context of neural implementations. A unified review of various "VLSI friendly" algorithms is also presented. The paper concludes with some conclusions drawn from the analysis of the implementations presented.

Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks

2020 ◽  
Vol 92 (11) ◽  
pp. 1263-1276
Author(s):  
Jiawei Xu ◽  
Yuxiang Huan ◽  
Yi Jin ◽  
Haoming Chu ◽  
Li-Rong Zheng ◽  
...  
Keyword(s):  
Neural Networks ◽  
Deep Neural Networks ◽  
Hardware Design

Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks

2020 ◽  
pp. 2150158
Author(s):  
Byungmin Ahn ◽  
Taewhan Kim
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Optimization Algorithm ◽  
State Of The Art ◽  
The State ◽  
Memory Access ◽  
Experimental Results ◽  
Hardware Platform ◽  
Access Latency ◽  
The Common

A new algorithm for extracting common kernels and convolutions to maximally eliminate the redundant operations among the convolutions in binary- and ternary-weight convolutional neural networks is presented. Precisely, we propose (1) a new algorithm of common kernel extraction to overcome the local and limited exploration of common kernel candidates by the existing method, and subsequently apply (2) a new concept of common convolution extraction to maximally eliminate the redundancy in the convolution operations. In addition, our algorithm is able to (3) tune in minimizing the number of resulting kernels for convolutions, thereby saving the total memory access latency for kernels. Experimental results on ternary-weight VGG-16 demonstrate that our convolution optimization algorithm is very effective, reducing the total number of operations for all convolutions by [Formula: see text], thereby reducing the total number of execution cycles on hardware platform by 22.4% while using [Formula: see text] fewer kernels over that of the convolution utilizing the common kernels extracted by the state-of-the-art algorithm.

scholarly journals Hardware Design for Smart Walking Stick Supporting Neural Networks

2019 ◽  
Vol 8 (12S) ◽  
pp. 407-410
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
System Design ◽  
Visually Impaired ◽  
Hardware Design ◽  
Hardware System ◽  
Visually Impaired People ◽  
Video Frames ◽  
Impaired People ◽  
Walking Stick

This paper aims to bring out the efficient hardware system design to be used in walking stick by the visually impaired people especially to support the cutting edge software technologies to assist in their mobility. It is designed in such a way that it is convenient to handle and also to perform heavier programs without any degradation in accuracy. Hardware design uses Rasberry pi3 Model B for finding the obstacle and to find the distance of the obstacle. Pi camera is used to capture the video frames and feed each frame for processing. For real time object detection, the proposed system uses neural network to train the images.

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