A fast placement and global routing integrated algorithm for hierarchical FPGAs

An early global routing framework for uniform wire distribution in SoCs

2016 29th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2016.7905454 ◽

2016 ◽

Author(s):

Bapi Kar ◽

Susmita Sur-Kolay ◽

Chittaranjan Mandal

Keyword(s):

Global Routing

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Hierarchical detailed floorplanning with global routing in VLSI layout design

Electronics and Communications in Japan (Part III Fundamental Electronic Science) ◽

10.1002/ecjc.4430741010 ◽

1991 ◽

Vol 74 (10) ◽

pp. 85-95

Author(s):

Michiroh Ohmura ◽

Shin'Ichi Wakabayashi ◽

Jun'Ichi Miyao ◽

Noriyoshi Yoshida

Keyword(s):

Layout Design ◽

Global Routing ◽

Vlsi Layout

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A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem

Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05 ◽

10.1145/1120725.1120786 ◽

2005 ◽

Cited By ~ 2

Author(s):

Tong Jing ◽

Ling Zhang ◽

Jinghong Liang ◽

Jingyu Xu ◽

Xianlong Hong ◽

...

Keyword(s):

Global Routing ◽

Routing Problem

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An interior point method for solving the global routing problem

10.1109/cicc.1989.56681 ◽

1989 ◽

Cited By ~ 3

Author(s):

A. Vannelli

Keyword(s):

Interior Point ◽

Interior Point Method ◽

Point Method ◽

Global Routing ◽

Routing Problem

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A New Global Routing Algorithm For FPGAs

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629817 ◽

2005 ◽

Cited By ~ 2

Author(s):

Yao-Wen Chang ◽

S. Thakur ◽

Kai Zhu ◽

D.F. Wong

Keyword(s):

Routing Algorithm ◽

Global Routing

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GRIP: Global Routing via Integer Programming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2010.2066030 ◽

2011 ◽

Vol 30 (1) ◽

pp. 72-84 ◽

Cited By ~ 26

Author(s):

Tai-Hsuan Wu ◽

Azadeh Davoodi ◽

Jeffrey T. Linderoth

Keyword(s):

Integer Programming ◽

Global Routing

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Fast placement-dependent full chip thermal simulation

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) ◽

10.1109/vtsa.2001.934531 ◽

2002 ◽

Cited By ~ 2

Author(s):

Zhiping Yu ◽

D. Yergeau ◽

R.W. Dutton ◽

S. Nakagawa ◽

J. Deeney

Keyword(s):

Thermal Simulation ◽

Fast Placement

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BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156492000060 ◽

1992 ◽

Vol 03 (01) ◽

pp. 137-170 ◽

Cited By ~ 4

Author(s):

MASSOUD PEDRAM ◽

ERNEST S. KUH

Keyword(s):

Shape Function ◽

Optimization Procedure ◽

University Of California ◽

Global Routing ◽

Top Down ◽

Function Computation ◽

Wide Range ◽

The University ◽

Linear Assignment ◽

Selection Of

This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top-down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques for satisfying a wide range of constraints (physical, topological, timing) and is, therefore, able to generate floorplans for a number of different layout styles. A systematic and efficient optimization procedure during the selection of suitable floorplan patterns that integrates floorplanning, global routing and pin assignment, a new pin assignment technique based on linear assignment and driven by the global routing solution and floorplan topology, and an effective timing-driven floorplanning scheme are among the other novel features of the floorplanner. These techniques have been incorporated in BEAR-FP, a macrocell layout system developed at the University of California, Berkeley. Results on various placement and floorplanning benchmarks are quite good.

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