FPGA Implementation of High Speed VLSI Architectures for AES Algorithm

2012 ◽  
Author(s):  
R.V. Kshirsagar ◽  
M.V. Vyawahare
Keyword(s):  
High Speed ◽  
Fpga Implementation ◽  
Vlsi Architectures ◽  
Aes Algorithm

scholarly journals FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures

2020 ◽  
Vol 9 (4) ◽  
pp. 549-551
Author(s):  
Somashekhar ◽  
◽  
Vikas Maheshwari ◽  
R. P. Singh ◽  
◽  
...  
Keyword(s):  
High Speed ◽  
Fault Tolerant ◽  
Source Code ◽  
Full Adder ◽  
Fpga Implementation ◽  
Vlsi Architectures

The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies.

scholarly journals A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2023
Author(s):  
Thanikodi Manoj Kumar ◽  
Kasarla Satish Reddy ◽  
Stefano Rinaldi ◽  
Bidare Divakarachari Parameshachari ◽  
Kavitha Arunachalam
Keyword(s):  
Data Security ◽  
High Speed ◽  
Fpga Implementation ◽  
Digital Data ◽  
Low Area ◽  
Aes Algorithm ◽  
Field Programmable ◽  
Hardware Architectures ◽  
Cyber Crimes ◽  
The Look

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

scholarly journals FPGA Implementation of Fault Tolerant Full Adder Design for High Speed VLSI Architectures

2019 ◽  
Vol 8 (2S3) ◽  
pp. 1325-1329
Keyword(s):  
High Speed ◽  
Fault Tolerant ◽  
Chip Thickness ◽  
Full Adder ◽  
Fpga Implementation ◽  
Use Of Self ◽  
Vlsi Architectures ◽  
The Everyday

The essential goal is to distinguish and diminish the deficiencies in full Adder configuration making use of Self checking and Self Repairing Adder Block. The tempo of chip disappointment is straightforwardly relative to chip thickness. A framework should be flaw tolerant to diminish the frustration rate. The nearness of different troubles can demolish the usefulness of complete snake. This paper displays a region proficient flaw tolerant complete snake shape that may repair issues without interfering with the everyday assignment of a framework. The combo and duplicate is finished through way of making use of Xilinx ISE 14.7 and actualized on FPGA Spartan three..

scholarly journals FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures

2020 ◽  
Vol 9 (4) ◽  
pp. 549-551
Keyword(s):  
High Speed ◽  
Fault Tolerant ◽  
Source Code ◽  
Full Adder ◽  
Fpga Implementation ◽  
Vlsi Architectures

The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies

AES-128 Cipher. High Speed, Low Cost FPGA Implementation

2007 ◽  
Author(s):  
Monica Liberatori ◽  
Fernando Otero ◽  
J. C. Bonadero ◽  
Jorge Castineira
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Fpga Implementation
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