Design and Implementation of High Speed, Low Area Multiported Loadless 4T Memory Cell

2011 ◽  
Author(s):  
Deepa Yagain ◽  
Ankit Parakh ◽  
Akriti Kedia ◽  
Gunjan Kumar Gupta
Keyword(s):  
High Speed ◽  
Memory Cell ◽  
Low Area ◽  
Design And Implementation

scholarly journals A VLSI DSP DESIGN AND IMPLEMENTATION OF ALL POLE LATTICE FILTER USING RETIMING METHODOLOGY

2012 ◽  
pp. 136-141
Author(s):  
PURU GUPTA ◽  
TARUN KUMAR RAWAT
Keyword(s):  
Signal Processing ◽  
Speech Processing ◽  
High Speed ◽  
Adaptive Filters ◽  
Clock Period ◽  
Transformation Technique ◽  
Low Area ◽  
Lattice Filters ◽  
Design And Implementation ◽  
Lattice Filter

All pole lattice fil ters are used in a variety of signal processing applications that is speech processing, adaptive filters and various other applications. The implementation of lattice f i l t e r requires more clock period hence low speed. There are various transformation technique pr es ent for design of high-speed or low-area or lowpower implementations. This paper presents design of high-speed (smaller clock period) implementation of 8th order all pole lattice filter using the methodology named as Retiming. Retiming reduces the clock period of the circuit, reducing the number of registers in the circuit, reducing the power consumption of the circuit. Therefore, retiming has been used to reduce the clock period of all pole lattice filters and it increases the speed of the system.

scholarly journals Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications

2021 ◽  
Vol 9 (12) ◽  
pp. 862-864
Author(s):  
Mutyala Sri Anantha Lakshmi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Description Language ◽  
Delay Reduction ◽  
Low Area ◽  
Booth Multiplier ◽  
Design And Implementation ◽  
Area Reduction ◽  
Hardware Description ◽  
Very High

Abstract: In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product

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