A novel, low voltage, precision CMOS current reference with no external components

2004 ◽  
Author(s):  
R. Dehghani ◽  
S.M. Atarodi
Keyword(s):  
Low Voltage ◽  
Current Reference

Low-voltage, High-precision Bandgap Current Reference Circuit

2012 ◽  
Vol 58 (6) ◽  
pp. 501
Author(s):  
ChongWei Keat ◽  
Jeevan Kanesan ◽  
Harikrishnan Ramiah
Keyword(s):  
High Precision ◽  
Low Voltage ◽  
Current Reference ◽  
Reference Circuit

scholarly journals Nano Power Current Reference Circuit Consisting of Sub-threshold CMOS Circuits

2019 ◽  
Vol 9 (1) ◽  
pp. 4657-4660
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Current Source ◽  
Threshold Power ◽  
Threshold Region ◽  
Voltage Range ◽  
Simulation Performance ◽  
Current Reference ◽  
Reference Circuit

a low voltage CMOS Nano power current reference circuit has been presented in this paper and also the circuit simulation performance in 180-nm UMC CMOS technology. Most of the MOSFETs operate in sub-threshold region consisting of bias-voltage, start-up and current-source sub-circuits. A stable reference current of 4-nA lying in supply voltage range of 1 V-1.8 V has been generated with line sensitivity of 0.203% /V. Within the temperature range of 0°C to 100 °C, and the voltage level of 1.8 V, the temperature coefficient was 7592ppm/°C. At the same voltage supply, the power dissipation was found out to be 380 NW. It is suitable to use this circuit in sub threshold power aware large scale integration.

scholarly journals Design low-voltage low-power current reference in 180nm - Diseño de un espejo de corriente a baja potencia y voltaje en 180nm

2020 ◽  
Vol 11 (3) ◽  
Author(s):  
Diego Fernando Jaramillo Calderon
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Room Temperature ◽  
Low Voltage ◽  
Circuit Simulation ◽  
The Body ◽  
Operating Voltage ◽  
Output Current ◽  
Current Reference ◽  
Body Bias

This paper describes design improvement of a current reference, originally based on dual-threshold voltage current mirror stages, these stages have been modified in order to improve the temperature dependence of the current of a diode-connected transistor and the figures of merit to compare this circuit both the base-circuit. The proposed solution has been designed in a 0.18 \text{\ensuremath{\mu}m} technology and analyzed through circuit simulation. Simulation results, when a body-bias generator is used, show an output current of 342 nA and a power consumption below 513 nW at the maximum operating voltage of 1.5 V and at the room temperature. The line sensitivity is 1 %/V, while the temperature coefficient is 17 ppm/°C. On the other hand, when the body-bias generator is neglected, the circuit shows an output current of 188 nA and a power consumption below 282 nW at the maximum operating voltage of 1.5V and at the room temperature. The line sensitivity is 2.89 %/V, while the temperature coefficient is 23 ppm/°C.  Resumen Hoy en día, los espejos de corriente o current reference, pueden ser mejorados con las características de inversión débil subthreshold-region cuando son construidos con tecnología CMOS, está tesis trata sobre cuatro estructuras de current reference basadas en un circuito de solo tres transistores, las figuras de merito como coeficiente de temperatura, consumo de potencia, y sensibilidad de carga y proceso son obtenidas en cada una de las estructuras, y posteriormente son comparadas para disernir cual de las implementaciones ha presentado un mejor desempeño. Las simulaciones fueron realizadas en una tecnología de 180 nm, nanómetros, TSMC CMOS usando transistores de tipo MEDIUM VOLTAGE THRESHOLD (MVT) para un voltaje máximo de alimentación de 2 y 3 voltios. La tesis esta compuesta de cuatro capítulos, el primero muestra los principios físicos para inducir una corriente cuando el transistor MOSFET se encuentra en la región de subthreshold, lineal y saturación. El segundo capitulo muestra las especificaciones tomadas en cuenta para implementar los cuatro diferentes diseños, como son el dimensionamiento y los parámetros eléctricos de las fuentes de alimentación, los diseños fueron implementados en Virtuoso de Cadence. El tercer capitulo muestra los resultados obtenidos en cada uno de los circuitos y una comparativa de las figuras de merito calculadas. Finalmente, el cuarto capitulo muestra las conclusiones de cada bloque, los beneficios obtenidos al implementar cada uno de los diseños así como la mejor solución acorde a las figuras de merito obtenidas. 

Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits

2017 ◽  
Vol 2 (1) ◽  
pp. 1-4
Author(s):  
Dinesh Kushwaha ◽  
D. K. Mishra
Keyword(s):  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Current Source ◽  
Cmos Technology ◽  
Threshold Region ◽  
Voltage Range ◽  
Current Reference ◽  
Reference Circuit

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration

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