scholarly journals Advanced process-based component integration in Telcordia's Cable OSS

2003 ◽  
Author(s):  
A.H.H. Ngu ◽  
D. Georgakopoulos ◽  
D. Baker ◽  
A. Cichocki ◽  
J. Desmarais ◽  
...  
Keyword(s):  
Component Integration

Automatic Generation of Hybrid Hw/Sw Applications by means of COTS Component Integration

2006 ◽  
Vol 4 (2) ◽  
pp. 93-99
Author(s):  
C. Vicente-Chicote ◽  
A. Toledo ◽  
C. Fernandez ◽  
P. Sanchez
Keyword(s):  
Automatic Generation ◽  
Component Integration

Real-time component integration based on transparent distribution

2005 ◽  
Vol 30 (4) ◽  
pp. 1-7
Author(s):  
Emilia Farcas ◽  
Claudiu Farcas ◽  
Wolfgang Pree ◽  
Josef Templ
Keyword(s):  
Real Time ◽  
Component Integration ◽  
Time Component

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

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