Coping with Variable Latency and Disorder in Distributed Event Streams

2006 ◽  
Author(s):  
R.S. Barga ◽  
G. Chkodrov
Keyword(s):  
Variable Latency

scholarly journals Buffer Placement and Sizing for High-Performance Dataflow Circuits

2022 ◽  
Vol 15 (1) ◽  
pp. 1-32
Author(s):  
Lana Josipović ◽  
Shabnam Sheikhha ◽  
Andrea Guerrieri ◽  
Paolo Ienne ◽  
Jordi Cortadella
Keyword(s):  
Performance Optimization ◽  
Optimization Model ◽  
High Performance ◽  
Control Flow ◽  
High Level Synthesis ◽  
Software Applications ◽  
Marked Graphs ◽  
Variable Latency ◽  
High Level ◽  
Strong Contrast

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches), unpredictable memory dependencies, and irregular control flow. Dataflow circuits exhibit an unconventional property: registers (usually referred to as “buffers”) can be placed anywhere in the circuit without changing its semantics, in strong contrast to what happens in traditional datapaths. Yet, although functionally irrelevant, this placement has a significant impact on the circuit’s timing and throughput. In this work, we show how to strategically place buffers into a dataflow circuit to optimize its performance. Our approach extracts a set of choice-free critical loops from arbitrary dataflow circuits and relies on the theory of marked graphs to optimize the buffer placement and sizing. Our performance optimization model supports important high-level synthesis features such as pipelined computational units, units with variable latency and throughput, and if-conversion. We demonstrate the performance benefits of our approach on a set of dataflow circuits obtained from imperative code.

Variable latency caches for nanoscale processor

2007 ◽  
Author(s):  
Serkan Ozdemir ◽  
Arindam Mallik ◽  
Ja Chun Ku ◽  
Gokhan Memik ◽  
Yehea Ismail
Keyword(s):  
Variable Latency

Adaptive variable-latency cache management for low-voltage caches

2014 ◽  
Author(s):  
Yung-Hui Yu ◽  
Po-Hao Wang ◽  
Tien-Fu Chen ◽  
Tay-Jyi Lin ◽  
Jinn-Shyan Wang
Keyword(s):  
Low Voltage ◽  
Cache Management ◽  
Variable Latency

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

2010 ◽  
Vol 18 (11) ◽  
pp. 1621-1624 ◽  
Author(s):  
Yiran Chen ◽  
Hai Li ◽  
Cheng-Kok Koh ◽  
Guangyu Sun ◽  
Jing Li ◽  
...  
Keyword(s):  
Low Power ◽  
Variable Latency
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