A New Buffer Cache Design Exploiting Both Temporal and Content Localities

2010 ◽  
Author(s):  
Jin Ren ◽  
Qing Yang
Keyword(s):  
Buffer Cache ◽  
Cache Design

scholarly journals AOIO: Application Oriented I/O Optimization for Buffer Management

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 573
Author(s):  
Xiaochang Li ◽  
Zhengjun Zhai ◽  
Xin Ye
Keyword(s):  
System Performance ◽  
Simulation Experiment ◽  
Buffer Management ◽  
Input Output ◽  
Output Data ◽  
Program Counter ◽  
Efficient Management ◽  
Management Scheme ◽  
Buffer Cache ◽  
Management Schemes

Emerging scale-out I/O intensive applications are broadly used now, which process a large amount of data in buffer/cache for reorganization or analysis and their performances are greatly affected by the speed of the I/O system. Efficient management scheme of the limited kernel buffer plays a key role in improving I/O system performance, such as caching hinted data for reuse in future, prefetching hinted data, and expelling data not to be accessed again from a buffer, which are called proactive mechanisms in buffer management. However, most of the existing buffer management schemes cannot identify data reference regularities (i.e., sequential or looping patterns) that can benefit proactive mechanisms, and they also cannot perform in the application level for managing specified applications. In this paper, we present an A pplication Oriented I/O Optimization (AOIO) technique automatically benefiting the kernel buffer/cache by exploring the I/O regularities of applications based on program counter technique. In our design, the input/output data and the looping pattern are in strict symmetry. According to AOIO, each application can provide more appropriate predictions to operating system which achieve significantly better accuracy than other buffer management schemes. The trace-driven simulation experiment results show that the hit ratios are improved by an average of 25.9% and the execution times are reduced by as much as 20.2% compared to other schemes for the workloads we used.

Breaking down memory walls

2020 ◽  
Vol 14 (3) ◽  
pp. 241-254
Author(s):  
Chen Luo ◽  
Michael J. Carey
Keyword(s):  
Memory Management ◽  
Storage Systems ◽  
Memory Allocation ◽  
Adaptive Memory ◽  
Component Structure ◽  
Memory Wall ◽  
Buffer Cache ◽  
Management Architecture

Log-Structured Merge-trees (LSM-trees) have been widely used in modern NoSQL systems. Due to their out-of-place update design, LSM-trees have introduced memory walls among the memory components of multiple LSM-trees and between the write memory and the buffer cache. Optimal memory allocation among these regions is non-trivial because it is highly workload-dependent. Existing LSM-tree implementations instead adopt static memory allocation schemes due to their simplicity and robustness, sacrificing performance. In this paper, we attempt to break down these memory walls in LSM-based storage systems. We first present a memory management architecture that enables adaptive memory management. We then present a partitioned memory component structure with new flush policies to better exploit the write memory to minimize the write cost. To break down the memory wall between the write memory and the buffer cache, we further introduce a memory tuner that tunes the memory allocation between these two regions. We have conducted extensive experiments in the context of Apache AsterixDB using the YCSB and TPC-C benchmarks and we present the results here.

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