Effects of using carrier aggregation with three component carriers in a mobile operator's network

2016 ◽  
Author(s):  
Madalina Oproiu ◽  
Vlad Boldan ◽  
Ion Marghescu
Keyword(s):  
Carrier Aggregation

Performance Evaluation of LTE-Advanced Heterogeneous Network Deployment Using Carrier Aggregation between Macro and Small Cells

2013 ◽  
Vol E96.B (6) ◽  
pp. 1297-1305
Author(s):  
Takahiro TAKIGUCHI ◽  
Kohei KIYOSHIMA ◽  
Yuta SAGAE ◽  
Kengo YAGYU ◽  
Hiroyuki ATARASHI ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Heterogeneous Network ◽  
Small Cells ◽  
Carrier Aggregation ◽  
Lte Advanced

Experiments on Asymmetric Carrier Aggregation Associated with Control Signaling Reception Quality in LTE-Advanced

2013 ◽  
Vol E96.A (11) ◽  
pp. 2106-2113
Author(s):  
Keisuke SAITO ◽  
Yuichi KAKISHIMA ◽  
Teruo KAWAMURA ◽  
Yoshihisa KISHIYAMA ◽  
Hidekazu TAOKA ◽  
...  
Keyword(s):  
Carrier Aggregation ◽  
Lte Advanced

scholarly journals Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park
Keyword(s):  
Integrated Circuit ◽  
Building Block ◽  
Orthogonal Frequency Division Multiplexing ◽  
Critical Path ◽  
Phase Error ◽  
System Level ◽  
Comb Filter ◽  
Carrier Aggregation ◽  
Path Delay ◽  
Front End

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

UE current consumption on carrier aggregation in LTE-A systems

2020 ◽  
Author(s):  
Juliano Joao Bazzo ◽  
Rayner de Melo Pires ◽  
Alvaro Javier Ortega ◽  
Navid Portela Salehi ◽  
Paulo Thiago Marreiros Santos
Keyword(s):  
Carrier Aggregation ◽  
Current Consumption
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