An energy efficient PAPR reduction technique for mobile terminals

2012 ◽  
Author(s):  
Byung Moo Lee ◽  
JinHyeock Choi ◽  
JongHo Bang ◽  
Byung-Chang Kang
Keyword(s):  
Energy Efficient ◽  
Reduction Technique ◽  
Papr Reduction ◽  
Mobile Terminals

scholarly journals AN IMPROVED PAPR REDUCTION TECHNIQUE FOR UNIVERSAL FILTER MULTI-CARRIER MODULATION

2018 ◽  
Vol 18 (1) ◽  
pp. 41-46 ◽  
Author(s):  
Pooja RANI ◽  
◽  
Silki BAGHLA ◽  
Himanshu MONGA ◽  
◽  
...  
Keyword(s):  
Reduction Technique ◽  
Papr Reduction ◽  
Universal Filter

scholarly journals Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-15
Author(s):  
Shadi Traboulsi ◽  
Valerio Frascolla ◽  
Nils Pohl ◽  
Josef Hausner ◽  
Attila Bilgic
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Reference Architecture ◽  
Least Significant Bit ◽  
Mobile Terminals ◽  
Standard Cell Library ◽  
Cell Library ◽  
Lte Advanced ◽  
Packet Data ◽  
Hardware Architectures

In this paper, we present and compare efficient low-power hardware architectures for accelerating the Packet Data Convergence Protocol (PDCP) in LTE and LTE-Advanced mobile terminals. Specifically, our work proposes the design of two cores: a crypto engine for the Evolved Packet System Encryption Algorithm (128-EEA2) that is based on the AES cipher and a coprocessor for the Least Significant Bit (LSB) encoding mechanism of the Robust Header Compression (ROHC) algorithm. With respect to the former, first we propose a reference architecture, which reflects a basic implementation of the algorithm, then we identify area and power bottle-necks in the design and finally we introduce and compare several architectures targeting the most power-consuming operations. With respect to the LSB coprocessor, we propose a novel implementation based on a one-hot encoding, thereby reducing hardware’s logic switching rate. Architectural hardware analysis is performed using Faraday’s 90 nm standard-cell library. The obtained results, when compared against the reference architecture, show that these novel architectures achieve significant improvements, namely, 25% in area and 35% in power consumption for the 128-EEA2 crypto-core, and even more important reductions are seen for the LSB coprocessor, that is, 36% in area and 50% in power consumption.

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