scholarly journals Tuning Stencil codes in OpenCL for FPGAs

2016 ◽  
Author(s):  
Qi Jia ◽  
Huiyang Zhou
Keyword(s):  
Stencil Codes

scholarly journals Stencil codes on a vector length agnostic architecture

2018 ◽  
Author(s):  
Adrià Armejach ◽  
Helena Caminal ◽  
Juan M. Cebrian ◽  
Rekai González-Alberquilla ◽  
Chris Adeniyi-Jones ◽  
...  
Keyword(s):  
Vector Length ◽  
Stencil Codes

Code Refinement of Stencil Codes

2014 ◽  
Vol 24 (03) ◽  
pp. 1441003 ◽  
Author(s):  
Marcel Köster ◽  
Roland Leißa ◽  
Sebastian Hack ◽  
Richard Membarth ◽  
Philipp Slusallek
Keyword(s):  
Programming Language ◽  
General Purpose ◽  
Peak Performance ◽  
Domain Specific Language ◽  
Competitive Performance ◽  
Specific Language ◽  
Popular Method ◽  
Domain Specific ◽  
Stencil Codes ◽  
Target Platform

A straightforward implementation of an algorithm in a general-purpose programming language does usually not deliver peak performance: Compilers often fail to automatically tune the code for certain hardware peculiarities like memory hierarchy or vector execution units. Manually tuning the code is firstly error-prone as well as time-consuming and secondly taints the code by exposing those peculiarities to the implementation. A popular method to avoid these problems is to implement the algorithm in a Domain-Specific Language (DSL). A DSL compiler can then automatically tune the code for the target platform. In this article we show how to embed a DSL for stencil codes in another language. In contrast to prior approaches we only use a single language for this task which offers explicit control over code refinement. This is used to specialize stencils for particular scenarios. Our results show that our specialized programs achieve competitive performance compared to hand-tuned CUDA programs while maintaining a convenient coding experience.

scholarly journals Loop Tiling in Large-Scale Stencil Codes at Run-Time with OPS

2018 ◽  
Vol 29 (4) ◽  
pp. 873-886 ◽  
Author(s):  
Istvan Z. Reguly ◽  
Gihan R. Mudalige ◽  
Michael B. Giles
Keyword(s):  
Large Scale ◽  
Loop Tiling ◽  
Run Time ◽  
Stencil Codes

scholarly journals LEVERAGING SHARED CACHES FOR PARALLEL TEMPORAL BLOCKING OF STENCIL CODES ON MULTICORE PROCESSORS AND CLUSTERS

2010 ◽  
Vol 20 (04) ◽  
pp. 359-376 ◽  
Author(s):  
MARKUS WITTMANN ◽  
GEORG HAGER ◽  
JAN TREIBIG ◽  
GERHARD WELLEIN
Keyword(s):  
High Speed ◽  
Distributed Memory ◽  
Multicore Processors ◽  
Memory Bandwidth ◽  
Performance Models ◽  
Shared Caches ◽  
Strong Scaling ◽  
Stencil Codes ◽  
Multicore Chips ◽  
Synthetic Modeling

Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach that makes explicit use of shared caches in multicore environments and minimizes synchronization and boundary overhead. Benchmark results are presented for three current x86-based microprocessors, showing clearly that our optimization works best on designs with high-speed shared caches and low memory bandwidth per core. We furthermore demonstrate that simple bandwidth-based performance models are inaccurate for this kind of algorithm and employ a more elaborate, synthetic modeling procedure. Finally we show that temporal blocking can be employed successfully in a hybrid shared/distributed-memory environment, albeit with limited benefit at strong scaling.

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