Temperature-dependent optimization of cache leakage power dissipation

2006 ◽  
Author(s):  
Peng Li ◽  
Yangdong Deng ◽  
L.T. Pileggi
Keyword(s):  
Power Dissipation ◽  
Leakage Power ◽  
Temperature Dependent ◽  
Leakage Power Dissipation

CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications

2021 ◽  
pp. 2250036
Author(s):  
Vijay Kumar Sharma
Keyword(s):  
Power Dissipation ◽  
Field Effect ◽  
Performance Metrics ◽  
Field Effect Transistors ◽  
High Current Density ◽  
Cylindrical Tube ◽  
Leakage Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Leakage Power Dissipation

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.

TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY

2014 ◽  
Vol 23 (05) ◽  
pp. 1450061 ◽  
Author(s):  
VIJAY KUMAR SHARMA ◽  
MANISHA PATTANAIK
Keyword(s):  
Threshold Voltage ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Deep Submicron ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Leakage Power Dissipation

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

scholarly journals Neutral leakage, power dissipation and pedestal fueling in open vs closed divertors

2020 ◽  
Vol 60 (7) ◽  
pp. 076011 ◽  
Author(s):  
L. Casali ◽  
D. Eldon ◽  
J.A. Boedo ◽  
T. Leonard ◽  
B. Covele
Keyword(s):  
Power Dissipation ◽  
Leakage Power ◽  
Leakage Power Dissipation

Thermal Mechanics Based Energy Efficient FIR Filter for Digital Signal Processing

2014 ◽  
Vol 612 ◽  
pp. 65-70 ◽  
Author(s):  
Bishwajeet Pandey ◽  
Tanesh Kumar ◽  
Teerath Das ◽  
S.M.M. Islam ◽  
Jagdish Kumar
Keyword(s):  
Ambient Temperature ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Digital Signal ◽  
Fir Filter ◽  
Leakage Power ◽  
Junction Temperature ◽  
High Profile ◽  
Thermal Mechanism ◽  
Leakage Power Dissipation

Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter. In this work, we are implementing FIR Filter on 28nm FPGA. After implementation of FIR Filter, we analyze the effect of in-built mechanism of Air Flow Controller and their produced Airflow on the junction temperature of FPGA. The mechanism of Ambient Temperature controller also play significant role in leakage power dissipation as well as junction temperature of FPGA. Finally, the mechanical structure of Hit Sink is considered for control of junction temperature of FPGA. There is 73.38% reduction in Leakage Power on 55 C ambient temperature when we increase airflow from 250 LFM to 500 LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 78.31% reduction in leakage power. There is 37.68% reduction in junction temperature of FPGA when we increase airflow from 250LFM to 500LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 41.76 % reduction in junction temperature on 45C ambient temperature. There is no effect of airflow on clock power. Whereas there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.

Leakage Minimization in CMOS VLSI Circuits

2016 ◽  
pp. 71-99
Author(s):  
Saurabh Chaudhury ◽  
Rohit Lorenzo
Keyword(s):  
Power Dissipation ◽  
High Performance ◽  
Detailed Comparison ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Circuit Techniques ◽  
Increasing Demand ◽  
Cmos Vlsi ◽  
Leakage Power Dissipation

Ever increasing demand for portable and battery-operated systems has lead to aggressive scaling. While technology scaling facilitates faster and high performance devices, at the same time it causes excessive power dissipation. Leakage power dissipation is now a dominating component of total power consumption in such portable devices. So there is a tremendous need to limit the power dissipation in high density chips which has initiated many innovative techniques to develop in the design of low power circuits and systems. Today's nano-scaled VLSI chips have ultra-thin gate oxide, very low threshold voltage and having short channels. As such leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. This Chapter review and compare the state of the art circuit techniques for leakage minimization. It also conceptually classifies the different techniques of leakage minimization. Moreover, a detailed comparison based on trading-offs with other design parameters is also given along with leakage minimization.

scholarly journals 9T SRAM CELL WITH MT-SVL TECHNIQUE FOR LEAKAGE POWER REDUCTION

2021 ◽  
Vol 9 (2) ◽  
pp. 1139-1143
Author(s):  
Kothamasu Jyothi, Et. al.
Keyword(s):  
Power Dissipation ◽  
Power Reduction ◽  
Leakage Power ◽  
Voltage Level ◽  
Technology Scaling ◽  
Sram Cell ◽  
Simulation Results ◽  
Leakage Power Dissipation

With the technology scaling there is a decrease in transistor size and increase in number of the transistors per a chip. It causes tremendous increase in complexity and the power dissipation of circuits. This paper mainly focuses on reduction of leakage power dissipation in SRAM 9T cells by employing multi threshold self controllable voltage level circuits  (LSVL & USVL). The Simulation results show that with the employment of MT-SVL technique, leakage power is being reduced compared to the improved SVL technique. The overall simulation is done with CMOS 180nm technology, using the tool of Cadence Virtuoso.

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