Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273) ◽

10.1109/iccd.1998.727079 ◽

2002 ◽

Cited By ~ 6

Author(s):

N. Narasimhan ◽

E. Teica ◽

R. Radhakrishnan ◽

S. Govindarajan ◽

R. Vemuri

Keyword(s):

Theorem Proving ◽

High Level Synthesis ◽

Resource Constrained ◽

High Level

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An in-place search algorithm for the resource constrained scheduling problem during high-level synthesis

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/1835420.1835422 ◽

2010 ◽

Vol 15 (4) ◽

pp. 1-13 ◽

Cited By ~ 5

Author(s):

Cheng-Juei Yu ◽

Yi-Hsin Wu ◽

Sheng-De Wang

Keyword(s):

Search Algorithm ◽

High Level Synthesis ◽

Scheduling Problem ◽

Resource Constrained ◽

Resource Constrained Scheduling Problem ◽

High Level

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Automatic Post-Synthesis Verification Support for a High Level Synthesis Step by using the HOL Theorem Proving System

Advances in Hardware Design and Verification - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35190-2_19 ◽

1997 ◽

pp. 291-308

Author(s):

Matthias Mutz

Keyword(s):

Theorem Proving ◽

High Level Synthesis ◽

Post Synthesis ◽

High Level

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Heuristic algorithm for the resource-constrained scheduling problem during high-level synthesis

IET Computers & Digital Techniques ◽

10.1049/iet-cdt:20070162 ◽

2009 ◽

Vol 3 (1) ◽

pp. 43 ◽

Cited By ~ 4

Author(s):

Y.-H. Wu ◽

C.-J. Yu ◽

S.-D. Wang

Keyword(s):

Heuristic Algorithm ◽

High Level Synthesis ◽

Scheduling Problem ◽

Resource Constrained ◽

Resource Constrained Scheduling Problem ◽

High Level

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Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) ◽

10.1109/codes-isss.2013.6659001 ◽

2013 ◽

Cited By ~ 3

Author(s):

Mingsong Chen ◽

Lei Zhou ◽

Geguang Pu ◽

Jifeng He

Keyword(s):

High Level Synthesis ◽

Resource Constrained ◽

Efficient Resource ◽

Oriented Parallel ◽

High Level

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Resource-Constrained Software Pipelining for High-Level Synthesis of DSP Systems

Algorithms and Parallel VLSI Architectures III ◽

10.1016/b978-044482106-5/50033-8 ◽

1995 ◽

pp. 377-388 ◽

Cited By ~ 3

Author(s):

F. Sánchez ◽

J. Cortadella

Keyword(s):

Software Pipelining ◽

High Level Synthesis ◽

Resource Constrained ◽

High Level ◽

Dsp Systems

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On the effectiveness of theorem proving guided discovery of formal assertions for a register allocator in a high-level synthesis system

Lecture Notes in Computer Science - Theorem Proving in Higher Order Logics ◽

10.1007/bfb0055147 ◽

1998 ◽

pp. 367-386 ◽

Cited By ~ 3

Author(s):

Naren Narasimhan ◽

Ranga Vemuri

Keyword(s):

Theorem Proving ◽

High Level Synthesis ◽

Synthesis System ◽

Guided Discovery ◽

High Level ◽

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Resource-constrained loop scheduling in high-level synthesis

Proceedings of the 43rd annual southeast regional conference on - ACM-SE 43 ◽

10.1145/1167253.1167300 ◽

2005 ◽

Author(s):

Rehab F. Abdel-Kader

Keyword(s):

High Level Synthesis ◽

Loop Scheduling ◽

Resource Constrained ◽

High Level

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Timing and resource constrained leakage power aware scheduling in high-level synthesis

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811939 ◽

2013 ◽

Author(s):

Nan Wang ◽

Cong Hao ◽

Nan Liu ◽

Haoran Zhang ◽

Takeshi Yoshimura

Keyword(s):

Leakage Power ◽

High Level Synthesis ◽

Resource Constrained ◽

High Level ◽

Power Aware Scheduling

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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