Functional VLSI design verification methodology for the CM-5 massively parallel supercomputer

2003 ◽  
Author(s):  
M. St. Pierre ◽  
S.-W. Yang ◽  
D. Cassiday
Keyword(s):  
Vlsi Design ◽  
Massively Parallel ◽  
Design Verification ◽  
Parallel Supercomputer ◽  
Verification Methodology

PARALLEL ACCELERATION ALGORITHM FOR SPIN MODELS

1992 ◽  
Vol 03 (04) ◽  
pp. 605-610 ◽  
Author(s):  
G.V. BHANOT ◽  
S.L. ADLER
Keyword(s):  
Massively Parallel ◽  
Xy Model ◽  
Spin Models ◽  
Cluster Algorithms ◽  
Multi Scale ◽  
Connection Machine ◽  
Parallel Supercomputer ◽  
Parallel Acceleration

We describe and implement a multi-scale acceleration algorithm for spin models on a massively parallel supercomputer, the Connection Machine CM-200. Unlike usual cluster algorithms, our algorithm is completely parallelizable. The time to update all variables in a system of volume Ld scales as Ld log 2L. We prove this by computing the time for one lattice sweep for the 2-d XY model for our algorithm on lattices of size up to 2048×2048.

scholarly journals Georgia Tech GT-VDAG VLSI Design Verification Document

1991 ◽  
Author(s):  
Sam H. Russ ◽  
Wei Siong Tan ◽  
Toshiro Kubota
Keyword(s):  
Vlsi Design ◽  
Design Verification ◽  
Georgia Tech
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