A VLSI module for IEEE floating-point multiplication/division/square root

2003 ◽  
Author(s):  
P.Y. Lu ◽  
K. Dawallu
Keyword(s):  
Floating Point ◽  
Square Root ◽  
Point Multiplication

scholarly journals A Mechanically Checked Proof of IEEE Compliance of the Floating Point Multiplication, Division and Square Root Algorithms of the AMD-K7™ Processor

1998 ◽  
Vol 1 ◽  
pp. 148-200 ◽  
Author(s):  
David M. Russinoff
Keyword(s):  
Register Transfer Level ◽  
The Other ◽  
Floating Point ◽  
Square Root ◽  
Rigorous Proof ◽  
Point Multiplication ◽  
Logical Operations ◽  
Other Hand ◽  
Ieee Standard ◽  
Proof Of Correctness

AbstractWe describe a mechanically verified proof of correctness of the floating point multiplication, division, and square root instructions of the AMD-K7 microprocessor. The instructions are implemented in hardware and represented here by register-transfer level specifications, the primitives of which are logical operations on bit vectors. On the other hand, the statements of correctness, derived from IEEE Standard 754, are arithmetic in nature and considerably more abstract. Therefore, we begin by developing a theory of bit vectors and their role in floating point representations and rounding. We then present the hardware model and a rigorous proof of its correctness. All of our definitions, lemmas and theorems have been formally encoded in the ACL2 logic, and every step in the proof has been mechanically checked with the ACL2 prover.

scholarly journals NULL Convention Floating Point Multiplier

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Digital Signal ◽  
High Dynamic Range ◽  
Floating Point ◽  
Single Precision ◽  
Critical Part ◽  
Point Multiplication ◽  
Null Convention Logic ◽  
High Dynamic

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

Efficient Floating -Point Square Root and Reciprocal Square Root Algorithms

2021 ◽  
Author(s):  
Leonid Moroz ◽  
Volodymyr Samotyy ◽  
Mariusz Wegrzyn ◽  
Ulyana Dzelendzyak
Keyword(s):  
Floating Point ◽  
Square Root
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