Exploiting Platform Heterogeneity for Power Efficient Data Centers

2007 ◽  
Author(s):  
Ripal Nathuji ◽  
Canturk Isci ◽  
Eugene Gorbatov
Keyword(s):  
Data Centers ◽  
Power Efficient ◽  
Efficient Data

scholarly journals Complicity of High-End SOC-FPGA’s for Data Centers

2021 ◽  
Vol 9 (6) ◽  
pp. 6-10
Author(s):  
Anil Kumar Retikal
Keyword(s):  
Data Analytics ◽  
Data Centers ◽  
Big Data Analytics ◽  
Low Latency ◽  
Data Streaming ◽  
Power Efficient ◽  
Efficient Data ◽  
High Bandwidth ◽  
Streaming Big Data

As the network traffic increasing significantly due to increase in Data streaming, Big Data Analytics, Cloud Computing, Increasing the load on Data Centers, Which leads to demand for high computational capabilities, low latency, high-bandwidth, power efficient data accelerators. As Re-Configurability of FPGA’s are more flexible for developing customized applications, so the FPGA hardware based data accelerators are the potential devices to achieve low latency and power efficient requirements. The modern FPGA’s are coming up with the embedded communication hard IP’s like PCIe, Ethernet, & DDR based memory controllers, which makes easy for the deployment of network attached FPGA’s in data centers. This paper presents the role of FPGA’s in datacenters and analysis of high-end FPGA’s by various vendors, which are suitable for deployment in data centers.

scholarly journals A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

2019 ◽  
Vol 8 (6S2) ◽  
pp. 876-882
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Design Methodology ◽  
Total Power ◽  
Data Path ◽  
Power Efficient ◽  
Efficient Data ◽  
Main Component ◽  
Static Logic ◽  
Important Design

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption

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