Smart Core System for Dependable Many-Core Processor with Multifunction Routers

2010 ◽  
Author(s):  
Shinya Takamaeda ◽  
Shimpei Sato ◽  
Takefumi Miyoshi ◽  
Kenji Kise
Keyword(s):  
Core System ◽  
Many Core

Performance Evaluation of Graph Partitioning on Many-core System

2021 ◽  
Author(s):  
Anuja A. Tapase ◽  
Siddheshwar V. Patil ◽  
Dinesh B. Kulkarni
Keyword(s):  
Performance Evaluation ◽  
Graph Partitioning ◽  
Core System ◽  
Many Core

A Fault-Tolerant Deflection Routing for Network-on-Chip

2016 ◽  
Vol 26 (03) ◽  
pp. 1750037 ◽  
Author(s):  
Xiaofeng Zhou ◽  
Lu Liu ◽  
Zhangming Zhu
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Deflection Routing ◽  
Core System ◽  
Routing Schemes ◽  
Routing Performance ◽  
Layout Area ◽  
On Chip ◽  
Many Core ◽  
Redundant Fault

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

scholarly journals Energy-Efficient Thread Mapping for Heterogeneous Many-Core Systems via Dynamically Adjusting the Thread Count

Energies ◽  
2019 ◽  
Vol 12 (7) ◽  
pp. 1346 ◽  
Author(s):  
Tao Ju ◽  
Yan Zhang ◽  
Xuejun Zhang ◽  
Xiaogang Du ◽  
Xiaoshe Dong
Keyword(s):  
Energy Efficiency ◽  
Energy Consumption ◽  
Prediction Model ◽  
Phase Changes ◽  
Core System ◽  
Computing Performance ◽  
Many Core ◽  
Thread Mapping ◽  
Intel Mic ◽  
Thread Count

Improving computing performance and reducing energy consumption are a major concern in heterogeneous many-core systems. The thread count directly influences the computing performance and energy consumption for a multithread application running on a heterogeneous many-core system. For this work, we studied the interrelation between the thread count and the performance of applications to improve total energy efficiency. A prediction model of the optimum thread count, hereafter the thread count prediction model (TCPM), was designed by using regression analysis based on the program running behaviors and heterogeneous many-core architecture feature. Subsequently, a dynamic predictive thread mapping (DPTM) framework was proposed. DPTM uses the prediction model to estimate the optimum thread count and dynamically adjusts the number of active hardware threads according to the phase changes of the running program in order to achieve the optimal energy efficiency. Experimental results show that DPTM obtains a nearly 49% improvement in performance and a 59% reduction in energy consumption on average. Moreover, DPTM introduces about 2% additional overhead compared with traditional thread mapping for PARSEC(The Princeton Application Repository for Shared-Memory Computers) benchmark programs running on an Intel MIC (Many integrated core)heterogeneous many-core system.

A Long-wire-connected and Multi-channel 3D Network-on-chip Design for Many-core System

2013 ◽  
Vol 11 (12) ◽  
Author(s):  
Tan Hai ◽  
Shahnawaz Talpur ◽  
Amir Mahmood Soomro ◽  
Chen Hong Mao
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Core System ◽  
3D Network ◽  
On Chip ◽  
Many Core
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