SmartMig: A Case for Page Migration and Self-Interleaving for On-Chip Distributed Memory Systems

2014 ◽  
Author(s):  
Weiwei Fu ◽  
Mingmin Yuan ◽  
Tianzhou Chen ◽  
Qingsong Shi ◽  
Li Liu ◽  
...  
Keyword(s):  
Distributed Memory ◽  
Memory Systems ◽  
Page Migration ◽  
On Chip

Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems

2014 ◽  
Vol 69 (3) ◽  
pp. 1491-1516 ◽  
Author(s):  
Weiwei Fu ◽  
Tianzhou Chen ◽  
Chao Wang ◽  
Li Liu
Keyword(s):  
Distributed Memory ◽  
Memory Systems ◽  
Memory Access ◽  
Thread Migration ◽  
On Chip

scholarly journals Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems

2019 ◽  
Vol 16 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Xiaoyuan Wang ◽  
Haikun Liu ◽  
Xiaofei Liao ◽  
Ji Chen ◽  
Hai Jin ◽  
...  
Keyword(s):  
Memory Systems ◽  
Hybrid Memory ◽  
Page Migration

Compiling for distributed-memory systems

1993 ◽  
Vol 81 (2) ◽  
pp. 264-287 ◽  
Author(s):  
H.P. Zima ◽  
B.M. Chapman
Keyword(s):  
Distributed Memory ◽  
Memory Systems

scholarly journals ParBiBit: Parallel tool for binary biclustering on modern distributed-memory systems

PLoS ONE ◽  
2018 ◽  
Vol 13 (4) ◽  
pp. e0194361 ◽  
Author(s):  
Jorge González-Domínguez ◽  
Roberto R. Expósito
Keyword(s):  
Distributed Memory ◽  
Memory Systems

scholarly journals Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

2022 ◽  
Vol 15 (2) ◽  
pp. 1-33
Author(s):  
Mikhail Asiatici ◽  
Paolo Ienne
Keyword(s):  
Large Scale ◽  
Sparse Matrix ◽  
Memory Systems ◽  
Graph Analytics ◽  
Matrix Vector Multiplication ◽  
Area Reduction ◽  
Cache Line ◽  
Speed Up ◽  
Memory Accesses ◽  
On Chip

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by requesting each cache line only once, even when there are multiple misses corresponding to it. However, such reuse mechanism is traditionally implemented using an associative lookup. This limits the number of misses that are considered for reuse to a few tens, at most. In this article, we present an efficient pipeline that can process and store thousands of outstanding misses in cuckoo hash tables in on-chip SRAM with minimal stalls. This brings the same bandwidth advantage as a larger cache for a fraction of the area budget, because outstanding misses do not need a data array, which can significantly speed up irregular memory-bound latency-insensitive applications. In addition, we extend nonblocking caches to generate variable-length bursts to memory, which increases the bandwidth delivered by DRAMs and their controllers. The resulting miss-optimized memory system provides up to 25% speedup with 24× area reduction on 15 large sparse matrix-vector multiplication benchmarks evaluated on an embedded and a datacenter FPGA system.

scholarly journals Combinatorial BLAS 2.0: Scaling combinatorial algorithms on distributed-memory systems

2021 ◽  
pp. 1-1
Author(s):  
Ariful Azad ◽  
Oguz Selvitopi ◽  
Md Taufique Hussain ◽  
John Gilbert ◽  
Aydin Buluc
Keyword(s):  
Distributed Memory ◽  
Memory Systems ◽  
Combinatorial Algorithms
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