An Efficient Reconfigurable Architecture Design and Implementation of Image Contrast Enhancement Algorithm

2012 ◽  
Author(s):  
Wen-Chieh Chen ◽  
Shih-Chia Huang ◽  
Trong-Yen Lee
Keyword(s):  
Contrast Enhancement ◽  
Image Contrast ◽  
Reconfigurable Architecture ◽  
Architecture Design ◽  
Design And Implementation ◽  
Image Contrast Enhancement ◽  
Enhancement Algorithm

Composite Image Contrast Enhancement Algorithm Based on Local Adaptive Stretching Window

2009 ◽  
Vol 29 (10) ◽  
pp. 2756-2761
Author(s):  
李成 Li Cheng ◽  
鞠明 Ju Ming ◽  
毕笃彦 Bi Duyan ◽  
刘波 Liu Bo
Keyword(s):  
Contrast Enhancement ◽  
Image Contrast ◽  
Composite Image ◽  
Image Contrast Enhancement ◽  
Enhancement Algorithm

Design and Implementation of Gain-Offset Correction Algorithm Hardware Architecture for Grayscale and Color Images Contrast Enhancement

2016 ◽  
Vol 25 (10) ◽  
pp. 1650120 ◽  
Author(s):  
Uche A. Nnolim
Keyword(s):  
Contrast Enhancement ◽  
High Speed ◽  
Low Cost ◽  
Correction Algorithm ◽  
Design And Implementation ◽  
Image Contrast Enhancement ◽  
Offset Correction ◽  
Time Requirements ◽  
Enhancement Algorithm ◽  
Processing Solution

This paper describes the design and implementation of a novel, high-speed hardware (HW) architecture for the gain-offset correction (GOC) image contrast enhancement algorithm on an FPGA fabric. The design is extremely fast and has been shown to process megapixel image frames at frame rates greatly exceeding real-time requirements. The design is small and compact enough to fit on small FPGAs to form a low-cost image processing solution. The automated nature of the contrast enhancement operation is due to the computation of global image statistics for each image. The architecture does not store any image frames to perform this task, heavily reducing memory requirements.

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