MMC02-3: DRPIT: Data-Rate PSNR Information Table Computation and Its Application for Variable Rate Video Streaming

2006 ◽  
Author(s):  
Harendra Narayan ◽  
Dilip Sarkar ◽  
James W. Modestino
2021 ◽  
Author(s):  
Andi Hasad ◽  
Muhammad Amin Bakri ◽  
Abdul Hafid Paronda ◽  
Sri Marini

VLSI Design ◽  
2002 ◽  
Vol 14 (4) ◽  
pp. 363-372 ◽  
Author(s):  
Eugene Grayver ◽  
Babak Daneshrad

A new flexible architecture is proposed for word-serial filtering and variable rate decimation/interpolation. The architecture is targeted for low power applications requiring medium to low data rate and is ideally suited for implementation on either an ASIC or an FPGA. It combines the small size and low power of an ASIC with the programmability and flexibility of a DSP. An efficient memory addressing scheme eliminates the need for power hungry shift registers and allows full reconfiguration. The decimation ratio, filter length and filter coefficients can all be changed in real time. The architecture takes advantage of coefficient symmetries in linear phase filters and in polyphase components.


2003 ◽  
Vol 21 (10) ◽  
pp. 1710-1720 ◽  
Author(s):  
C.E. Luna ◽  
Y. Eisenberg ◽  
R. Berry ◽  
T.N. Pappas ◽  
A.K. Katsaggelos

2012 ◽  
Vol 2 (2) ◽  
pp. 134-136
Author(s):  
Ch. Divya Ch. Divya ◽  
◽  
Dr. P. Govardhan Dr. P. Govardhan

Sign in / Sign up

Export Citation Format

Share Document