Fast IP packet classification with configurable processor

The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.

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A Novel IP Packet Classification Algorithm Based on CrossProduct and Hash Tree

2006 6th International Conference on ITS Telecommunications ◽

10.1109/itst.2006.288764 ◽

2006 ◽

Author(s):

Lei Yu ◽

Yaping Deng ◽

Jiangbo Wang ◽

Chaoyong Jiang ◽

Ke Yin

Keyword(s):

Packet Classification ◽

Classification Algorithm ◽

Ip Packet

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Packet Classification by Multilevel Cutting of the Classification Space: An Algorithmic-Architectural Solution for IP Packet Classification in Next Generation Networks

Journal of Computer Systems Networks and Communications ◽

10.1155/2008/603860 ◽

2008 ◽

Vol 2008 ◽

pp. 1-14

Author(s):

Motasem Aldiab ◽

Emi Garcia-Palacios ◽

Danny Crookes ◽

Sakir Sezer

Keyword(s):

High Power ◽

Differentiated Services ◽

Packet Classification ◽

Next Generation Networks ◽

The Internet ◽

Quality Requirements ◽

Content Addressable Memories ◽

High Power Consumption ◽

Ip Packet ◽

Dynamic Updates

Traditionally, the Internet provides only a “best-effort” service, treating all packets going to the same destination equally. However, providing differentiated services for different users based on their quality requirements is increasingly becoming a demanding issue. For this, routers need to have the capability to distinguish and isolate traffic belonging to different flows. This ability to determine the flow each packet belongs to is called packet classification. Technology vendors are reluctant to support algorithmic solutions for classification due to their nondeterministic performance. Although content addressable memories (CAMs) are favoured by technology vendors due to their deterministic high-lookup rates, they suffer from the problems of high-power consumption and high-silicon cost. This paper provides a new algorithmic-architectural solution for packet classification that mixes CAMs with algorithms based on multilevel cutting of the classification space into smaller spaces. The provided solution utilizes the geometrical distribution of rules in the classification space. It provides the deterministic performance of CAMs, support for dynamic updates, and added flexibility for system designers.

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