Analysing the behaviour of distributed software architectures: a case study

2002 ◽  
Author(s):  
J. Magee ◽  
J. Kramer ◽  
D. Giannakopoulou
Keyword(s):  
Software Architectures ◽  
Distributed Software

On the use of connector libraries in distributed software architectures

2002 ◽  
Vol 27 (1) ◽  
pp. 45-52
Author(s):  
Bharath Kumar M ◽  
Y. N. Srikant ◽  
Lakshminarayanan R
Keyword(s):  
Software Architectures ◽  
Distributed Software

scholarly journals A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level

2012 ◽  
Vol 2012 ◽  
pp. 1-16 ◽  
Author(s):  
Anthony Barreteau ◽  
Sébastien Le Nours ◽  
Olivier Pasquier
Keyword(s):  
Performance Evaluation ◽  
Computation Method ◽  
Software Architectures ◽  
System Architectures ◽  
Modeling Approach ◽  
Simulation Speed ◽  
First Case ◽  
Execution Model ◽  
Transaction Level

Abstract models are necessary to assist system architects in the evaluation process of hardware/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance evaluation and fast exploration of the design space. In this paper, we present a specific transaction level modeling approach for performance evaluation of hardware/software architectures. This approach relies on a generic execution model that exhibits light modeling effort. Created models are used to evaluate by simulation expected processing and memory resources according to various architectures. The proposed execution model relies on a specific computation method defined to improve the simulation speed of transaction level models. The benefits of the proposed approach are highlighted through two case studies. The first case study is a didactic example illustrating the modeling approach. In this example, a simulation speed-up by a factor of 7,62 is achieved by using the proposed computation method. The second case study concerns the analysis of a communication receiver supporting part of the physical layer of the LTE protocol. In this case study, architecture exploration is led in order to improve the allocation of processing functions.

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