Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA

2010 ◽  
Author(s):  
Ghizlane Lhairech-Lebreton ◽  
Philippe Coussy ◽  
Eric Martin
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
High Level Synthesis ◽  
High Level

scholarly journals High-level Synthesis for Low-power Design

2015 ◽  
Vol 8 (0) ◽  
pp. 12-25 ◽  
Author(s):  
Zhiru Zhang ◽  
Deming Chen ◽  
Steve Dai ◽  
Keith Campbell
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
High Level Synthesis ◽  
High Level

scholarly journals Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 73
Author(s):  
Francesco Ratto ◽  
Tiziana Fanni ◽  
Luigi Raffo ◽  
Carlo Sau
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Systems Design ◽  
Hardware Acceleration ◽  
High Level Synthesis ◽  
Clock Gating ◽  
Technology Application ◽  
Positive Effects ◽  
High Level ◽  
Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

Data path allocation for low power in high-level synthesis

2000 ◽  
Author(s):  
Yu H. Zheng ◽  
Ching C. Jong ◽  
Hongwei Zhu
Keyword(s):  
Low Power ◽  
High Level Synthesis ◽  
Data Path ◽  
High Level
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