scholarly journals Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner Using FPGA Devices and a High Level Synthesis Tool

2011 ◽  
Author(s):  
Zhong-Ho Chen ◽  
Alvin W.Y. Su ◽  
Ming-Ting Sun ◽  
Scott Hauck
Keyword(s):  
High Resolution ◽  
High Level Synthesis ◽  
Synthesis Tool ◽  
High Level

scholarly journals High-level Synthesis Integrated Verification

2015 ◽  
Vol 5 (5) ◽  
pp. 864-870
Author(s):  
M. Dossis
Keyword(s):  
Great Proportion ◽  
Experimental Work ◽  
Integrated Approach ◽  
High Level Synthesis ◽  
Ic Design ◽  
Program Code ◽  
Design Synthesis ◽  
Design Project ◽  
Synthesis Tool ◽  
High Level

It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author.  Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures

2021 ◽  
Author(s):  
Rui Li ◽  
Lincoln Berkley ◽  
Yihang Yang ◽  
Rajit Manohar
Keyword(s):  
High Level Synthesis ◽  
Synthesis Tool ◽  
Complex Program ◽  
High Level
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